DDR Memory Data Transfer Mechanism for Glitch-Free Rank Switching
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Solution Overview
Problem
Conventional memory devices face timing margin reduction and latency issues due to signal delays, particularly at high frequencies, leading to setup and hold time conflicts and glitches during rank-to-rank switching in DDR and SDR DRAM systems.
Innovation Solution
A data transfer mechanism and switching sequence for memory devices that utilize a FIFO component, digital delay line, and clock control to improve timing margins and reduce latency, enabling glitch-less delay line switching and efficient rank-to-rank switching without halting data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional delay line is used to delay clock signals, then signal delay is achieved, but timing margins are reduced and setup/hold time conflicts occur at high frequencies
Solution Approach 1:
A FIFO buffer is introduced as an intermediary component between the input clock signal and the delayed clock signal. The FIFO buffer absorbs timing variations and provides stable data transfer across clock domains, preventing setup and hold time violations that would otherwise occur at high frequencies.
Solution Approach 2:
The patent replaces the conventional mechanical/gate-based delay line with a digital FIFO-based timing adjustment mechanism. This substitution eliminates the timing margin reduction problem inherent in traditional delay lines while maintaining the ability to delay clock signals by a predetermined period.
2Adaptability or versatility
If delay line settings are changed during operation, then adaptability is improved, but glitches occur in the output signal
Solution Approach 1:
The patent implements a preliminary action by stopping the input clock signal to the delay line before changing delay settings. This ensures that no new signals are processed during the transition, preventing glitches in the output. After the setting change, the clock signal is resumed, maintaining signal stability throughout the adaptation process.
3Adaptability or versatility
If rank-to-rank switching is performed in memory systems, then memory access flexibility is improved, but latency increases due to waiting for stable clock output
Solution Approach 1:
The patent maintains continuity of useful action by allowing the FIFO buffer to continue operating during rank-to-rank switching. Data transfer through the FIFO buffer proceeds without interruption, eliminating the need to wait for stable clock output before switching ranks, thus reducing access latency while maintaining switching flexibility.
4Speed
If conventional delay lines are used, then signal delay is achieved, but device complexity increases due to multiple gates and control logic
Solution Approach 1:
The FIFO buffer serves multiple functions simultaneously: it delays clock signals, absorbs timing variations, provides clock domain crossing, and prevents glitches during setting changes. This multi-functionality replaces what would otherwise require separate dedicated circuits for each function, reducing overall device complexity.
Data Source
AI summary
Various embodiments described herein provide for a data transfer mechanism for a memory device, such as a Double Data Rate (DDR) memory device, which can improve critical timing within the memory device without a latency impact. In addition, various embodiments described herein provide for a switching sequence for a memory device, which can improve switching time for the memory device.