DDR Memory Interface Circuit Tri-Stating Unused Data Bus Drivers
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Solution Overview
Problem
Current DDR memory systems waste power during write operations as all data drivers are active, even if not all are needed, leading to inefficient power consumption, especially in battery-powered devices.
Innovation Solution
A memory interface circuit that selectively disables unused data bus drivers during write operations using write driver mask information and OR-gate logic to determine which drivers need to transmit, implementing mid-point termination structures for DDR receivers to improve signal integrity and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all data drivers are kept active during DDR write operations, then data transmission reliability is ensured, but power consumption increases unnecessarily
Solution Approach 1:
The patent applies local quality by enabling only the specific data drivers that correspond to the active memory columns being written to, while keeping other drivers in high-impedance state. This is achieved through column address decoding that activates only the necessary driver circuits, thereby reducing overall power consumption while maintaining reliable data transmission for the active columns.
Solution Approach 2:
The patent implements partial action by activating only the subset of data drivers that are actually needed for the current write operation, rather than keeping all drivers active. The write enable signals are selectively applied to only those drivers corresponding to the active columns, avoiding unnecessary power consumption from idle drivers while ensuring complete coverage of required data paths.
2Quantity of substance
If all data drivers are activated during write operations, then complete data coverage is ensured, but unnecessary power is consumed by unused drivers
Solution Approach 1:
The patent enables only the specific data drivers corresponding to active memory columns through selective write enable signaling. Each data driver is locally controlled based on whether its associated column is being written to, ensuring complete coverage of required data paths while eliminating power waste from inactive drivers.
Solution Approach 2:
The patent segments the data driver array into independently controllable groups based on column addresses. By decoding the column address and generating selective write enable signals, the system divides the monolithic driver activation into discrete, manageable segments, allowing precise control over which drivers are active and reducing overall power consumption.
3Reliability
If data drivers remain active continuously, then signal integrity is maintained, but battery life is reduced
Solution Approach 1:
The patent implements periodic activation of data drivers based on actual write operation requirements. Drivers are activated only during the brief periods when their associated columns are being written to, and placed in high-impedance state during idle periods. This periodic on-demand activation maintains signal integrity when needed while dramatically extending battery life by eliminating continuous power consumption.
Solution Approach 2:
The patent applies partial action by activating data drivers only for the duration and scope actually required by the memory write operation. Rather than continuous activation, drivers are enabled partially and temporarily only when column write operations are pending, ensuring signal integrity for active operations while conserving battery power during idle periods.
Data Source
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AI summary
A memory interface circuit includes a plurality of data bus drivers and logic adapted to be operatively responsive to write driver mask information. If desired, the plurality of bus drivers and the logic may be implemented in separate integrated circuits. The plurality of bus drivers are adapted to be responsive to a write operation. The logic is also adapted to disable any one of the plurality of data bus drivers based on the write driver mask information during the write operation.