DDR Memory Module With Redefined Pin Definitions For 32 IC Chips
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Solution Overview
Problem
Current motherboards with two memory module slots are limited in the number of IC chips they can support, making it difficult to expand beyond the capacity of older motherboards with four slots, leading to a need for an improved double data rate memory solution.
Innovation Solution
A double data rate memory configuration with at least 32 integrated circuit chips and two read-only memories, utilizing a circuit board with a goldfinger connection interface and redefining standard pin definitions to enable effective operation of more IC chips, specifically using 10 pins with 'NC' definitions for additional capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of IC chips is increased to 32 or more in a single memory module, then the memory capacity is improved, but the pin capacity according to old DDR SDRAM specifications becomes insufficient
Solution Approach 1:
The patent changes the pin capacity parameter by redefining the pin definitions according to JEDEC standards. Specifically, pins that were previously defined for other functions are reassigned to support additional IC chips. This parameter change allows the same physical connector to support 32 or more IC chips by utilizing the pin capacity more efficiently and differently than older specifications
Solution Approach 2:
The goldfinger connection interface is designed to serve multiple functions by supporting both traditional memory operations and the extended IC chip configurations. The pin definitions are made multi-functional, allowing the same pins to support different chip arrangements and configurations, thereby achieving universality across different memory capacities
2Area of stationary object
If motherboards are designed with only two memory module slots to reduce size, then the motherboard area is reduced, but the maximum memory expandability is limited compared to four-slot motherboards
Solution Approach 1:
The patent increases the density of IC chips within a single memory module by moving from traditional 16-chip configurations to 32-chip or higher configurations. This dimensional change in chip arrangement density allows a single module to provide the capacity that previously required multiple modules, compensating for the reduced number of slots while maintaining expandability
3Productivity
If standard pin definitions are redefined to support more IC chips, then the pin capacity utilization is improved, but compatibility with old DDR SDRAM specifications is reduced
Solution Approach 1:
The patent applies parameter changes by systematically redefining pin definitions according to updated JEDEC standards. This allows the system to achieve higher pin capacity utilization while maintaining a standardized approach that ensures compatibility through adherence to recognized industry standards
Data Source
AI summary
A double data rate memory includes a circuit board, a goldfinger connection interface, at least 16 first IC chips, at least 16 second IC chips, a first and a second read-only memory. The circuit board has a first surface, a second surface, a first region and a second region. The first IC chips are disposed on the first surface. The second IC chips are disposed on the second surface. The first read-only memory is connected with the first and the second IC chips disposed on the first region. The second read-only memory is connected with the first and the second IC chips disposed on the second region. 10 pins of the goldfinger connection interface are connected with the second read-only memory and the first and the second IC chips disposed on the second region to make them operate. At least 32 IC chips are effectively operated in single one memory.