DDR Nonvolatile Memory Timing Skew Calibration
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Solution Overview
Problem
Current technologies lack a suitable method for reliable high-speed data transfer in nonvolatile memory systems, particularly for double data rate (DDR) nonvolatile NAND flash memory, due to the challenge of precise alignment and synchronization between data signals and data strobe signals, which becomes increasingly difficult as device speeds and component density rise.
Innovation Solution
A system and method that establish a range of delay values between data signals and a data strobe signal for optimal alignment, using a training portion in the nonvolatile memory to write and read known data patterns at different delay values, determining the optimal delay value for subsequent operations to ensure central alignment and minimize timing skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device speeds and component density increase to improve productivity, then data transfer speed is improved, but timing alignment precision deteriorates
Solution Approach 1:
The patent performs delay training and timing alignment calibration before actual high-speed data transfer operations. A training portion is written with known data patterns at various delay values, and the optimal delay is determined in advance through comparison operations, allowing subsequent high-speed transfers to use pre-determined optimal timing parameters.
Solution Approach 2:
The patent implements adjustable delay circuits that can dynamically modify the delay value of data strobe signals based on detected timing skew. The system can adaptively change delay parameters during different operational phases (training vs. normal operation) and even adjust for variations due to temperature, voltage, and process conditions.
2Reliability
If delay training is performed to improve timing alignment precision, then data transfer reliability is improved, but processing time increases
Solution Approach 1:
The patent divides the memory into a training portion and a normal data portion. The training portion is specifically designated for delay training operations using known data patterns, while the rest of the memory maintains normal high-speed operation. This segmentation allows training to occur in a dedicated area without impacting overall system performance.
Solution Approach 2:
The patent performs delay training on only a portion of the memory (the training portion) rather than the entire memory space. Known data patterns are written to and read from this specific training area to determine optimal delay values, avoiding the time cost of training the entire memory while still achieving system-wide timing optimization.
3Manufacturing precision
If multiple delay values are tested to determine optimal alignment, then timing alignment precision is improved, but the number of operations increases
Solution Approach 1:
The patent tests multiple delay values (both earlier and later than the expected optimal value) to ensure the true optimal delay is captured. By writing known data patterns at various delay values and comparing readings, the system identifies the precise delay that provides central alignment, even though this requires more operations than a single-delay test.
Data Source
AI summary
The subject system and method are generally directed to ensuring reliable high speed data transfer in multiple data rate nonvolatile memory, such as double data rate (DDR) nonvolatile NAND flash memory and the like. The system and method provide measures to achieve read and write training for data signals (DQ) and the data strobe signal (DQS), one relative to the other. In such manner, high speed data transfers to and from nonvolatile memory such as flash devices may be performed with a reduced risk of data loss even at high operational frequencies.