DDR Nonvolatile Memory Hybrid Row Buffer Architecture
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Solution Overview
Problem
Current storage devices, such as Double Data Rate (DDR) SDRAM, provide improvements in performance but lack permanent storage capabilities, necessitating faster solutions for storing and transferring large amounts of data in computing systems.
Innovation Solution
The implementation of a Double Data Rate (DDR) nonvolatile memory architecture that supports data transfers on both the rising and falling edges of each clock cycle, incorporating direct access registers for coherent data and page buffers for non-coherent data, allowing for efficient data storage and retrieval while maintaining compatibility with legacy flash functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DDR SDRAM is used to improve data transfer speed, then bandwidth is increased, but permanent storage capability is lost
Solution Approach 1:
The memory system is segmented into multiple independent memory banks, each capable of autonomous operation. This allows the system to provide both high-speed access to active data in DDR SDRAM banks and permanent storage in non-volatile memory banks simultaneously, resolving the contradiction between speed and persistence by separating these functions into distinct segments.
Solution Approach 2:
The patent merges DDR SDRAM technology with non-volatile memory (NVM) into a unified memory structure. This combination creates a hybrid memory system that exhibits both the high-speed characteristics of DDR SDRAM and the permanent storage capabilities of NVM, allowing the system to achieve both improved bandwidth and data persistence within the same memory array.
2Ease of operation
If legacy flash functions are maintained for compatibility, then ease of operation is improved, but device complexity increases
Solution Approach 1:
The memory device is designed with multi-functionality to serve both traditional flash memory roles and DDR memory roles. By implementing a unified interface that can operate in both legacy flash modes and DDR modes, the device maintains compatibility with existing systems while providing enhanced performance, thereby improving ease of operation without requiring separate dedicated hardware for different memory types.
Solution Approach 2:
The memory device includes integrated control logic that automatically manages the complexity of supporting both legacy and DDR operations. The device self-configures and self-manages the different operational modes, bank selections, and protocol handling, thereby shielding the user from the underlying complexity while maintaining full legacy compatibility and DDR performance.
Data Source
AI summary
A Double Data Rate (DDR) nonvolatile memory includes a DDR I/F block to receive an address that is used to separate DDR data into coherent data and non-coherent data that are stored separately in the DDR nonvolatile memory.