DDR NVM Express Read Sequencing for High-Temperature Memory Access
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Solution Overview
Problem
Conventional DRAM memory solutions are unsuitable for high-temperature environments due to performance degradation and high power consumption, while SRAM offers faster speeds but at a higher cost and power draw, necessitating a more efficient memory access solution for such conditions.
Innovation Solution
Implementing a nonvolatile memory (NVM) device with a reduced command sequence and a DDR interface compatible with the LPDDR4 standard, allowing for express access operations using NVR command pairs that output data at a double data rate, reducing the number of clock cycles required for read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for memory access in high-temperature applications, then acceptable access speeds can be achieved, but performance degrades and power consumption increases at high temperatures
Solution Approach 1:
The patent transitions from volatile memory (DRAM/SRAM) to nonvolatile memory (NVM), fundamentally changing the operational parameters and temperature characteristics of the memory system. This parameter change enables reliable operation in high-temperature environments where DRAM performance degrades, while maintaining fast access speeds through optimized command sequences and DDR interface protocols
2Speed
If SRAM is used to replace DRAM for high-temperature applications, then faster access speeds are achieved, but component cost and power consumption increase significantly
Solution Approach 1:
The patent employs nonvolatile memory devices that can be manufactured at lower cost compared to SRAM, while providing sufficient performance for the application. The NVM devices use standard manufacturing processes and interface protocols (LPDDR4 compatible) that reduce system cost, eliminating the need for expensive SRAM components
3Adaptability or versatility
If conventional DRAM command sequences are used, then standard compatibility is maintained, but the number of clock cycles required for read operations is excessive
Solution Approach 1:
The patent segments the memory access operation into optimized command sequences specifically designed for nonvolatile memory characteristics. By dividing the read operation into targeted command pairs (READ1/READ2) with specific timing relationships, the system achieves faster access times while maintaining compatibility with standard DDR interface protocols through careful sequencing and timing control
4Quantity of substance
If standard DRAM read operations with burst length of 16 or 32 are used, then data transfer capacity is sufficient, but data loss occurs when cache memory size is smaller than the burst length
Solution Approach 1:
The patent implements dynamic control of burst length and command sequencing based on cache memory size and application requirements. The system can adaptively adjust the number of data beats transferred and the timing of command pairs to match the specific cache capacity, ensuring that data is transferred in optimal chunks without exceeding cache boundaries and causing data loss
Data Source
AI summary
A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.