DDR Memory Output Control Circuit DLL Delay Compensation
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining data output synchronization with high-frequency system clocks and varying operation environments, such as voltage levels, temperature, and process changes, which can lead to reduced operation reliability and data output margin.
Innovation Solution
A data output control circuit that generates output signals corresponding to both rising and falling edges of the system clock, using a DLL clock to compensate for internal delays, and activates control signals in a sequence that maintains a constant operation margin without additional delay units, ensuring data output synchronization across different environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the system clock frequency is increased to improve data input/output speed, then productivity is improved, but the operation margin and reliability deteriorate due to internal delays and synchronization issues
Solution Approach 1:
A DLL clock is introduced as an intermediary signal between the system clock and the data output control circuit. The DLL clock is phase-aligned with the system clock but allows for independent delay adjustment, serving as a mediator that resolves the synchronization conflict between high-speed operation and internal delay compensation
Solution Approach 2:
The delay of the DLL clock relative to the system clock is adjusted as a variable parameter to compensate for internal delays in the data output path. By dynamically changing the delay parameter, the circuit maintains synchronization margin even at high clock frequencies where fixed delay circuits would fail
2Reliability
If additional delay units are added to compensate for internal delays and maintain synchronization, then reliability is improved, but device complexity increases
Solution Approach 1:
The DLL clock serves multiple functions simultaneously: it provides the timing reference for data output, compensates for internal delays, and maintains phase alignment with the system clock. This multi-functionality eliminates the need for separate delay compensation circuits, reducing overall device complexity while improving reliability
3Reliability
If delay locked loop (DLL) circuit is used to compensate for internal delays, then data output synchronization is improved, but device complexity and power consumption increase
Solution Approach 1:
The delay compensation function is extracted from the main data output control logic and implemented through a separate DLL clock signal. This separation allows the DLL to be optimized independently and eliminates the need for complex delay adjustment circuits within the data output path itself
Data Source
AI summary
A semiconductor memory device using system clock with a high frequency can maintain a constant operation margin even in the change of operation environments including voltage level, temperature, and process. The semiconductor memory device includes an output control signal generator configured to be responsive to a read pulse that is activated in response to a read command, to generate an odd number of first output source signals corresponding to a rising edge of a system clock and a even number of second output source signals corresponding to a falling edge of the system clock, and an output enable signal generator configured to generate a first rising enable signal and a falling enable signal on the basis of the first output source signal and generate a second rising enable signal on the basis of the second output source signal, according to column address strobe (CAS) latencies, the first rising enable signal being activated earlier than the second rising enable signal by a half cycle of the system clock.