DDR Output Driver Slew-Rate Control With Shared Sub-Drivers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices, particularly those using DDR interfaces, the mismatch in pull-up and pull-down current drive capabilities of output drivers leads to a decreased data valid window, and the need to control slew rates to prevent signal integrity degradation, while maintaining high drive capabilities is challenging due to reduced power supply voltage and the difficulty in achieving fine-line designs.
Innovation Solution
The semiconductor device incorporates a configuration with shared selectors and slew rate controllers that selectively apply slew-rate control signals to sub-drivers, allowing for equal slew rates and adjusting drive capabilities by combining sub-drivers, thereby merging the functions of sub-driver selection and slew rate control into a single transistor, reducing the need for separate transistors and minimizing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the sizes of transistors Tr1 to Tr3 are increased to maintain high current drive capabilities, then the current drive capabilities are improved, but it becomes difficult to achieve a fine-line semiconductor device
Solution Approach 1:
The patent merges the functions of transistor Tr1 (sub-driver enable), Tr2 (output data control), and Tr3 (slew rate control) into a single transistor. This consolidation eliminates the need for multiple large transistors while maintaining both high current drive capability and fine-line design compatibility, directly resolving the contradiction between power and manufacturing precision
Solution Approach 2:
The single transistor in the invention performs multiple functions simultaneously: it acts as a sub-driver enable switch, output data control element, and slew rate control mechanism. This multi-functionality allows the device to achieve high current drive capability without requiring multiple separate transistors, thus enabling fine-line design
2Ease of operation
If transistor Tr3 is used to dominantly control the slew rate, then the slew rate control is improved, but the sizes of transistors Tr1 and Tr2 need to be equal to or larger than Tr3, increasing area
Solution Approach 1:
The patent combines the slew rate control function (previously requiring transistor Tr3) with the sub-driver enable and output data control functions into a single transistor. This merger eliminates the need for separate slew rate control transistors while maintaining effective slew rate control, thereby reducing the total transistor area
3Adaptability or versatility
If multiple transistors Tr1, Tr2, and Tr3 are connected in series to compose an output driver, then the drive capability and slew rate control are achieved, but the device complexity increases
Solution Approach 1:
The patent merges multiple transistors (Tr1, Tr2, Tr3) into a single transistor that performs all necessary functions: sub-driver enable, output data control, and slew rate control. This simplification reduces device complexity while maintaining the adaptability to adjust drive capability through selective connection of sub-drivers
4Reliability
If the slew rate is increased to maintain output data valid window, then the data valid window is preserved, but power supply noise and signal reflection increase
Solution Approach 1:
The patent enables dynamic adjustment of the slew rate by controlling the single transistor's operation. This allows the system to optimize the slew rate for each output transition, maintaining the output data valid window while minimizing power supply noise and signal reflection by avoiding excessively high slew rates
Data Source
AI summary
A semiconductor device includes a core circuit including an integrated circuit; output drivers, each including sub-drivers to output digital data transferred from the core circuit, as output data; and a selector that selects a sub-driver to be driven from among the plurality of sub-drivers. Each of the sub-drivers includes: an output transistor connected between a first power supply and an output wiring line to allow the output data to rise or fall according to the digital data; and a switching transistor and a slew-rate control transistor which are connected in series between a gate of the output transistor and a second power supply. The switching transistor turns on or off the output transistor according to the digital data. A gate potential adjusted to determine a slew rate for rise or fall of the output data is selectively provided by the selector to each slew-rate control transistor.