Shared Output Driving Circuit for DDR CRC and Parity Signals

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Solution Overview

Problem

Semiconductor devices, particularly DDR2, DDR3, and DDR4, face challenges in efficiently outputting internal information such as Cyclic Redundancy Checks (CRC) and command/address parity to external devices due to evolving specifications and increased operation speeds, which require new circuit components and operations.

Innovation Solution

The semiconductor device incorporates an information generation circuit, an information multiplexing circuit, and an information driving circuit to output internal information to an external device, utilizing PMOS and NMOS transistors to drive output pads in different operation modes, enabling efficient output and precharge operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a dedicated driving circuit is added for each new specification (CRC, parity, DBI), then the device can comply with new specifications, but the device complexity increases

Engineering Contradiction:
Improvecompliance with new specificationsVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The driving circuit is designed to perform multiple functions by selectively outputting different information types (internal information such as CRC/parity or normal data) through the same output pad. The circuit uses control signals to determine whether to output internal information generated by the semiconductor device or normal data from memory cells, eliminating the need for separate dedicated circuits for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If internal information is always output through separate dedicated circuits, then specification compliance is ensured, but the output timing is delayed and operational efficiency decreases

Engineering Contradiction:
Improvespecification complianceVSAvoidoutput timing
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the output path for internal information (CRC, parity) and normal data into a single shared output pad and driving circuit. By combining these previously separate output paths, the device can efficiently manage output timing and reduce delays while still ensuring reliable output of internal information when required by specifications.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If separate circuits are used for internal information output and normal data output, then each function is optimized, but the overall device complexity and component count increase

Engineering Contradiction:
Improvefunction optimizationVSAvoidcomponent count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The driving circuit is designed with dynamic switching capability, allowing it to adapt its function based on control signals. The circuit can dynamically switch between outputting internal information (when specification compliance is required) and normal data (during regular operations), providing function optimization without requiring separate dedicated circuits for each mode.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8922257B2Semiconductor device including driving circuit
Publication Date: 2014.12.30 SK HYNIX INC
  • US8922257B2 patent drawing
  • US8922257B2 patent drawing
  • US8922257B2 patent drawing

AI summary

A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.