DDR Memory Packet Processing with Descriptor Integration
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Solution Overview
Problem
Network devices face inefficiencies in packet processing due to separate storage and reading of packet entities (PKT) and packet descriptors (PD) in different memory types, leading to increased design costs and wiring pressure, as well as low reading efficiency.
Innovation Solution
Storing both packets and packet descriptors in the same DDR memory by dividing it into blocks with separate storage spaces, allowing for simultaneous storage and reading of packets and PDs, thereby optimizing memory utilization and reducing design costs and wiring complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PD is stored in QDR SRAM and PKT is stored in DDR SDRAM separately, then the packet processing can be performed, but the design cost increases and wiring pressure increases
Solution Approach 1:
The patent merges the storage of PD and PKT into a single DDR memory by allocating different memory regions: the first memory region stores PKT while the second memory region stores PD. This consolidation eliminates the need for separate QDR SRAM for PD storage, thereby reducing design cost and wiring pressure while maintaining packet processing capability.
2Device complexity
If PD and PKT are read separately in two steps, then the storage structure is simple, but the reading efficiency is low
Solution Approach 1:
The patent enables continuous reading of PD and PKT by storing them in the same DDR memory with adjacent or logically connected memory addresses. The network device can continuously access both PD and PKT without switching between different memory types, eliminating idle time and improving reading efficiency while keeping the storage structure relatively simple.
3Speed
If PD is stored in QDR SRAM, then the access speed to PD is fast, but the design cost increases
Solution Approach 1:
The patent replaces the expensive QDR SRAM with DDR memory for storing PD. Although DDR memory has lower raw access speed compared to QDR SRAM, the overall system performance is improved by eliminating the need for expensive QDR SRAM hardware while maintaining adequate access speed through optimized memory management and continuous access patterns.
Data Source
AI summary
A memory of a network device is divided into first blocks, each first block being divided into second blocks, and each second block including a first storage space and second storage space. When a packet is stored, second blocks occupied by the packet are determined based on a packet length and a first storage space length, and the packet is stored into a first storage space of each of the second blocks. For each of the second blocks, a PD corresponding to the second block is generated, and stored into a second storage space of the second block. When a packet is read, the second blocks to be read are determined based on a start address of the packet. A packet fragment is read from a first storage space of the second blocks to be read, and the read packet segments are composed into the second packet to be sent.