DDR On-Die Parity Storage for Multi-Level Error Correction
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Solution Overview
Problem
Existing error correction methods for dynamic random-access memory (DRAM) devices face inefficiencies due to the use of either too many or too few parity bits, leading to either wastage of memory or inadequate error detection/correction capabilities.
Innovation Solution
A multi-level error correction method is employed, involving primary and secondary coding to generate transitional symbols and inner codes, which are stored on-die, allowing for efficient error detection and correction by a host computing system using erasure decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more parity bits are used for error correction, then error detection and correction capability is improved, but memory capacity is wasted
Solution Approach 1:
The patent segments the error correction process into multiple stages: first generating transitional symbols from data bits, then generating inner codes from these transitional symbols. This segmentation allows efficient use of parity bits by processing data in hierarchical layers rather than applying uniform error correction to all bits simultaneously.
Solution Approach 2:
The patent introduces a new dimension in error correction by creating transitional symbols that represent groups of data bits, then applying parity bits to these symbols rather than directly to individual data bits. This dimensional transformation from bit-level to symbol-level processing optimizes the ratio of parity bits to protected data.
2Quantity of substance
If fewer parity bits are used, then memory capacity is preserved, but error detection and correction capability deteriorates
Solution Approach 1:
The patent changes the parameters of error correction by using variable-length transitional symbols (e.g., 8-bit symbols from 64 data bits) and configuring parity bits to protect these symbols rather than individual bits. This parameter transformation allows achieving the same or better error protection with fewer total parity bits.
Solution Approach 2:
The patent performs preliminary encoding to generate transitional symbols before applying parity bit protection. This preliminary action organizes data into structured units that are more efficiently protected by subsequent parity bits, maximizing the protective coverage of each parity bit.
3Device complexity
If traditional ECC methods are used, then implementation is simple, but accuracy in identifying error locations deteriorates
Solution Approach 1:
The patent introduces transitional symbols as intermediaries between data bits and parity bits. These symbols serve as mediators that carry encoded information about groups of data bits, enabling more accurate error location identification while maintaining relatively simple implementation through standard encoding operations.
Solution Approach 2:
The patent performs preliminary generation of transitional symbols that embed location information about the underlying data bits. This preliminary encoding action prepares the data structure to facilitate precise error location identification during the decoding phase, improving measurement precision without proportionally increasing complexity.
Data Source
AI summary
The described technology provides a multi-level error correction method, including encoding data received from a double data rate (DDR) memory by performing primary coding to generate transitional symbols, wherein the primary coding comprising at least one of cyclical redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding, performing a secondary coding on the transitional symbols to generate inner codes, the inner codes comprising code 1 parities generated from the transitional symbols and code 2 parities generated from the transitional symbols and metadata stored on the DDR memory, wherein the secondary coding comprising Reed Solomon (RS) encoding, and saving the inner codes on parity bit storage locations on a die of the DDR memory.