DDR SDRAM Phase Calibration Circuit for LPDDR4 Compliance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
DDR SDRAM physical layer circuits fail to meet the phase difference requirements of the LPDDR4 standard, particularly due to temperature and voltage variations affecting the phase difference between data input/output signals and data strobe signals.
Innovation Solution
A memory signal phase difference calibration circuit and method that includes a multiphase clock generator, calibration control circuit, access control circuit, comparison circuit, and phase controller to adjust and calibrate the phase difference between data input/output signals and data strobe signals within a DDR SDRAM physical layer circuit, using a calibration mode to ensure compliance with LPDDR4 standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a constant phase difference of 90 degrees is used between DQ and DQS signals, then compliance with DDR4 and LPDDR3 standards is achieved, but compliance with LPDDR4 standard is not met
Solution Approach 1:
The patent implements dynamic phase difference adjustment by introducing a calibration circuit that can modify the phase difference between DQ and DQS signals based on operating conditions. The calibration control circuit adjusts the phase of the target signal (DQ or DQS) dynamically during calibration mode, transitioning from a fixed 90-degree phase difference to an adjustable range (200-800 ps) to meet LPDDR4 requirements while maintaining compatibility with other DDR standards.
Solution Approach 2:
The patent changes the phase difference parameter from a fixed value (90 degrees) to a variable parameter that can be adjusted within a specific range (200-800 ps). The calibration control circuit modifies this parameter based on temperature and voltage conditions, allowing the system to adapt to different DDR standards and environmental variations by changing the phase difference parameter dynamically.
2Device complexity
If the phase difference between DQ and DQS is kept constant, then circuit design is simple, but temperature and voltage variations cause phase difference drift outside LPDDR4 specifications
Solution Approach 1:
The patent implements preliminary calibration action by introducing a calibration mode that executes before normal operation. The calibration control circuit performs preliminary adjustment of the phase difference based on predetermined calibration data, establishing optimal phase settings before the system encounters temperature and voltage variations during actual operation, thereby preventing phase drift outside specifications.
Solution Approach 2:
The patent implements feedback mechanisms through the calibration control circuit that monitors phase difference variations and adjusts the target signal phase accordingly. The comparison circuit compares calibration data with actual signal phases and feeds back adjustment information to the calibration control circuit, creating a closed-loop system that maintains phase difference stability under temperature and voltage variations.
Data Source
AI summary
A memory signal phase difference calibration circuit includes: a clock generator providing clocks allowing a physical layer (PHY) circuit of DDR SDRAM to generate a data input/output signal (DQ) and a data strobe signal (DQS) for accessing a storage circuit; a calibration control circuit outputting a phase control signal according to an adjustment range to adjust the phase of a target signal (DQ or DQS), and outputting a calibration control signal; an access control circuit reading storage data representing predetermined data from the storage circuit according to the calibration control signal; a comparison circuit comparing the predetermined data with the storage data to output a result allowing the calibration control circuit to alter the adjustment range accordingly; and a phase controller outputting a clock control signal according to the phase control signal to set the phase of a target clock used for the PHY circuit generating the target signal.