DDR PHY Parallel Clock Paths for Low-Latency Clock Switching
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Solution Overview
Problem
Existing clock switching systems experience latency due to the time required for delay control circuits to lock onto new clock signals, leading to interruptions in data traffic flow during clock switching operations.
Innovation Solution
The implementation of parallel clock paths with respective delay control circuits allows for alternating clock sources and delay control signals, reducing latency by ensuring the delay control circuits lock onto new signals before switching, thereby minimizing the impact of locking latency on clock switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single clock path is used with delay control circuits to switch between clock sources, then the system structure remains simple, but clock switching latency increases due to the time required for delay control circuits to lock onto new clock signals
Solution Approach 1:
The single clock path is divided into two parallel clock paths (first clock path and second clock path), each with its own delay control circuit. This segmentation allows the system to switch between clock sources without requiring one delay control circuit to re-lock, as the other path remains ready with its delay control circuit already locked to its clock source.
Solution Approach 2:
The delay control circuit in the non-active clock path performs preliminary locking to its clock source in advance. This preliminary action ensures that when a clock switch is needed, the standby delay control circuit is already locked and ready, eliminating the locking latency that would otherwise occur during the switch.
2Productivity
If parallel clock paths with respective delay control circuits are implemented, then clock switching latency is reduced, but the device complexity increases due to additional clock paths and control circuits
Solution Approach 1:
The first and second clock paths are merged into a unified clock distribution system that shares common components such as the multiplexer and output distribution network. This merging approach reduces the overall complexity compared to having completely separate systems, while still maintaining the benefits of parallel delay control circuits for rapid switching.
3Reliability
If clock switching is performed without parallel paths, then the device structure remains simple, but data traffic flow is interrupted during the switching process
Solution Approach 1:
The parallel clock path architecture ensures continuous useful action by maintaining both clock paths operational simultaneously. When switching between clock sources, the system transitions from one active path to the other without interrupting the clock signal delivery, thereby maintaining continuous data traffic flow without gaps or interruptions.
Data Source
AI summary
A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.