DDR PHY Voltage Regulator With Staggered MOSFET Current Boost
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing voltage regulators for Double Data Rate (DDR) Physical Interfaces (PHY) circuits face challenges in maintaining a stable regulated voltage during read requests, leading to voltage drops that can reduce read margin and data accuracy.
Innovation Solution
A voltage regulator system that utilizes staggered current sources, enabled by delay component-specific signals, and an auxiliary regulator that tracks process, voltage, and temperature (PVT) variations and frequency changes, to provide a regulated voltage that matches the dynamic requirements of DDR PHY circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional voltage regulator with a single MOSFET is used to supply regulated voltage to DDR PHY, then the circuit structure is simple, but voltage drops occur during read requests due to amplifier transient response
Solution Approach 1:
The voltage regulator is segmented into multiple parallel MOSFETs (first MOSFET, second MOSFET, third MOSFET, fourth MOSFET) each controlled by separate enable signals. This segmentation allows independent control of current supply timing, preventing voltage drops during read requests while maintaining a relatively simple overall structure.
Solution Approach 2:
The enable signals are generated in advance based on predicted read request timing. The first enable signal is generated when a read request is predicted, and the second enable signal is generated when a read request is confirmed, allowing the voltage regulator to prepare current supply before the actual read operation occurs.
2Quantity of substance
If the capacitive load is increased to supply sufficiently large regulated voltage, then the regulated voltage can be maintained, but the voltage still drops during sudden large changes in load current
Solution Approach 1:
The voltage regulator performs preliminary action by generating enable signals in advance based on predicted read request timing. The first MOSFET is activated when a read request is predicted, and the second MOSFET is activated when confirmed, ensuring current supply is prepared before the load current changes occur, thus preventing voltage drops.
Solution Approach 2:
The voltage regulator uses feedback by monitoring the regulated voltage and adjusting the enable signals accordingly. When a read request is detected, the feedback mechanism triggers the generation of enable signals to activate additional MOSFETs, compensating for the load current changes and maintaining voltage stability.
Data Source
AI summary
A voltage regulator provides a regulated voltage to a double data rate (DDR) Physical Interface (PHY) including a plurality of delay elements. The voltage regulator includes: an amplifier, for receiving a voltage at a first input terminal and generating an output voltage; a first MOSFET coupled to a supply voltage and a second input terminal of the amplifier; a second MOSFET coupled in parallel with the first MOSFET for generating a first current in response to a first enable signal; a load, coupled to the first MOSFET and the second MOSFET, for generating the regulated voltage; and a load capacitor, coupled in parallel with the load. The first enable signal is generated by inputting a gate enable signal for a delay element of the plurality of delay elements into a delay circuit corresponding to the delay element.