DDR PSRAM Data Strobe Signal Timing Control
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Solution Overview
Problem
Conventional DDR PSRAM controllers face challenges in accurately masking the impedance period of the data strobe signal due to variable wait states and potential drifts in clock cycles, leading to invalid data latching during read operations.
Innovation Solution
The implementation of a DDR PSRAM with a data receiver, address decoder, and data strobe generating unit that receives single and double data rate signals via a common bus, allowing for precise timing and synchronization using a data strobe signal to toggle and latch data without a low-impedance period, enabling direct use of both rising and falling edges of the strobe signal for data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable wait states are used to enhance data transfer flexibility, then adaptability is improved, but timing accuracy deteriorates due to clock cycle drifts
Solution Approach 1:
A data strobe signal is introduced as an intermediary between the clock signal and the data latching operation. The strobe signal explicitly marks the valid data period, serving as a mediator that bridges the flexibility of variable wait states with the precision required for accurate data sampling, eliminating the need to mask impedance periods
Solution Approach 2:
The patent changes the timing parameter reference from fixed clock edges to a dynamic data strobe signal that adapts to variable wait states. This parameter change allows the system to maintain timing accuracy despite variations in wait state duration, as the strobe signal is generated based on actual data readiness rather than fixed clock cycles
2Adaptability or versatility
If impedance period masking is implemented to handle variable wait states, then adaptability is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent extracts and eliminates the complex impedance period masking mechanism by using a data strobe signal instead. The strobe signal directly indicates when data is valid without requiring additional control logic to mask or unmask impedance periods, thereby reducing device complexity while maintaining adaptability to variable wait states
3Productivity
If data strobe signal is used for double data rate transfer, then productivity is improved, but measurement precision requirements increase due to edge timing sensitivity
Solution Approach 1:
The data strobe signal is generated self-consistently within the memory device based on actual data readiness, rather than relying on external timing references. This self-service approach ensures that the strobe edges are inherently synchronized with data validity, meeting timing precision requirements without adding external complexity
Data Source
AI summary
A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory. The DDR PSRAM also includes a data transmitter and a data strobe generating unit. The data transmitter obtains data stored in the address of the memory and provides a double data rate data to the controller according to the obtained data, and the data strobe generating unit a data strobe signal to the controller and toggling the data strobe signal in response to the double data rate data.