DDR Input Sampling Circuit With Extended CS Timing Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-frequency DDR DRAMs, the pulse width of the C/A signal and CS signal decreases due to process, voltage, and temperature variations, leading to skew and potential failure in C/A sampling as the valid pulse width of the C/A signal after the CS signal end cannot be collected.
Innovation Solution
A signal processing circuit broadens the pulse width of the CS signal backward to ensure the end moment of the valid signal in the first CS signal is later than the end moment of the C/A signal, using a clock pulse signal for accurate sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the DRAM is increased to improve productivity, then the operating speed increases, but the pulse width of the C/A signal and CS signal decreases, causing timing skew and sampling failures
Solution Approach 1:
The patent applies preliminary action by extending the pulse width of the CS signal in advance before the sampling point. This ensures that even when timing skew occurs at high frequencies, the extended CS signal pulse will still cover the C/A signal valid period, allowing the sampling circuit to correctly capture the data without failure
Solution Approach 2:
The patent changes the temporal parameter of the CS signal by extending its pulse width backward in time. This parameter modification creates a time margin that compensates for the timing skew between the C/A and CS signals, ensuring reliable sampling at high DRAM frequencies
2Speed
If the pulse width of C/A signal and CS signal is reduced due to process, voltage and temperature variation, then the operating frequency can be increased, but the valid signal duration decreases, causing the end moment of C/A signal to be later than CS signal, leading to sampling failure
Solution Approach 1:
The patent performs preliminary action by extending the CS signal pulse width backward in time before the sampling point. This creates a time buffer that ensures the extended CS signal will still be valid when the C/A signal arrives, even though the C/A signal ends later due to reduced pulse width from PVT variations
Solution Approach 2:
The patent applies beforehand cushioning by creating a time margin through pulse width extension. This cushion compensates for the uncertainty in timing caused by PVT variations, ensuring that the CS signal remains valid throughout the entire period when the C/A signal is valid, preventing sampling failures
Data Source
AI summary
An input sampling system and method, a storage medium, and a computer device involve: a signal processing circuit configured to receive an initial chip select signal and a command/address signal, and broaden a pulse width of a valid signal in the initial chip select signal backward to obtain a first chip select signal, to control an end moment of a valid signal in the first chip select signal to be later than an end moment of a valid signal in the command/address signal; and an input sampling circuit connected to the signal processing circuit, and configured to receive the command/address signal, the first chip select signal, and a clock pulse signal and sample the command/address signal according to the first chip select signal and the clock pulse signal.