DDR SDRAM Signal Calibration Circuit for Voltage and Temperature Adaptation
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Solution Overview
Problem
DDR SDRAM signal calibration systems face challenges in adapting to voltage and temperature variations, leading to incorrect data sampling due to misalignment of the DQS signal preamble, which is exacerbated in LPDDR SDRAM, causing early or late sampling and resulting in incorrect or incomplete data read.
Innovation Solution
A DDR SDRAM signal calibration device comprising an enablement signal setting circuit, a signal gating circuit, and a calibration circuit that generates and adjusts the DQS enablement setting signal to produce a gated DQS signal, first and second delay signals, and calibration signals to maintain or adjust the DQS enablement setting, ensuring accurate sampling by realigning the DQS signal with the reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the DQS enablement setting is fixed based on initial calibration, then the device can operate correctly under initial conditions, but it cannot adapt to voltage and temperature variations causing sampling errors
Solution Approach 1:
The patent implements dynamic calibration by introducing a calibration circuit that continuously monitors the DQS signal and adjusts the DQS enablement setting in real-time. The calibration circuit generates calibration signals that dynamically modify the enablement timing based on detected signal characteristics, transforming a static fixed setting into a dynamic adaptive system that responds to voltage and temperature variations.
Solution Approach 2:
The patent employs feedback mechanisms where the calibration circuit samples the DQS signal and uses the sampled information to generate calibration signals that adjust the DQS enablement setting. This closed-loop feedback system continuously monitors signal integrity and self-corrects timing deviations, enabling the system to adapt to environmental changes without external intervention.
2Measurement precision
If the preamble position is used to set DQS enablement timing, then sampling can be synchronized initially, but the position variation with voltage/temperature causes sampling to occur at wrong timing
Solution Approach 1:
The patent applies preliminary action by performing calibration operations before actual data sampling. The calibration circuit预先 (in advance) detects the DQS signal characteristics and adjusts the enablement setting to compensate for anticipated variations. This preliminary calibration ensures that subsequent sampling operations occur at the correct timing even when voltage or temperature changes occur during operation.
Solution Approach 2:
The patent implements parameter changes by modifying the DQS enablement timing parameters based on calibration results. The calibration circuit detects variations in signal characteristics and dynamically adjusts timing parameters such as enablement start time, duration, and level transitions. This parameter adaptation allows the system to maintain precise sampling timing despite changes in operating conditions.
3Loss of time
If a delay signal from previous DQS_EN signal is sampled to determine early DQS signal, then timing can be adjusted, but the interval between read operations may be too long to sample the delay signal
Solution Approach 1:
The patent ensures continuity of useful action by maintaining the calibration functionality across multiple read operations. Instead of requiring a new calibration cycle for each read operation, the system preserves calibration state and continues using it for subsequent operations. This continuous approach eliminates time loss from repeated calibration while ensuring timing accuracy is maintained throughout the data reading process.
4Measurement precision
If the tristate of DQS signal is pulled up to sample delay signal, then timing can be detected, but noise influence makes the sampling result unreliable
Solution Approach 1:
The patent introduces an intermediary calibration circuit that mediates between the DQS signal and the sampling operation. Instead of directly sampling the potentially noisy tristate signal, the calibration circuit first processes the DQS signal through controlled delay paths and level adjustments, creating a cleaner intermediate signal that is then sampled. This intermediary processing stage filters out noise while preserving the essential timing information.
Data Source
AI summary
Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.