DQS Enable Timing Calibration in DDR SDRAM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In Double Data Rate (DDR) SDRAM memory systems, aligning read command and data on bidirectional buses is challenging due to varying delays caused by system configuration and operating conditions, leading to indeterminate data strobe clock signals and timing drift, which existing solutions like programmable, feedback, and external GATEON methods fail to address effectively.
Innovation Solution
A method involving a read delay determination circuit and a DQS enable circuit that measures the read delay between a memory controller and a DDR SDRAM by writing a Gray code sequence, sampling returned data signals, and using a lookup table to determine the optimal DQS enable timing, allowing for dynamic adjustment and drift compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed timing is used for DQS enable signal, then device complexity is reduced, but timing alignment precision deteriorates due to varying system delays
Solution Approach 1:
The patent implements dynamic adjustment of the DQS enable signal timing by measuring the actual read delay between memory controller and memory device, then using this measured delay to dynamically position the DQS enable signal within the preamble period. This replaces fixed timing with adaptive timing that responds to actual system conditions, resolving the contradiction between simplicity and precision.
Solution Approach 2:
The patent employs a feedback mechanism where the read delay is measured and used to adjust the DQS enable timing. The system continuously monitors the timing relationship and adjusts the enable signal position based on the measured delay, creating a closed-loop control system that maintains precise timing alignment despite variations in system configuration and operating conditions.
2Measurement precision
If dynamic adjustment of DQS enable timing is implemented, then timing alignment precision is improved, but device complexity increases due to additional measurement and control circuits
Solution Approach 1:
The patent implements a self-service mechanism where the system measures its own read delay and automatically adjusts the DQS enable timing without external intervention. The memory controller performs the delay measurement and uses the result to autonomously position the enable signal, eliminating the need for complex external calibration equipment or manual adjustment mechanisms.
Solution Approach 2:
The patent performs the delay measurement and timing adjustment during system initialization before normal operation begins. By completing the timing calibration in advance, the system establishes optimal timing parameters that can then be used during normal operation without requiring continuous complex adjustments, reducing the overall complexity burden.
3Device complexity
If initialization sample is taken at fixed time after read command, then device complexity is reduced, but measurement precision of read delay deteriorates
Solution Approach 1:
The patent implements dynamic sampling where the initialization sample is taken at a time that is predetermined relative to the read command but allows for variation based on measured delays. This dynamic sampling approach adapts to different system configurations and operating conditions, maintaining measurement precision without requiring overly complex sampling control logic.
Data Source
AI summary
A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.