Multi-Stage DDR Serializer for Memory IO Above 10 Gbps
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Solution Overview
Problem
Traditional serialization techniques fail to meet the increasing input and output data rate requirements of advanced memory devices, particularly with specifications like GDDR5× requiring data rates above 10 Gbps, where the serializer component is a speed-critical bottleneck.
Innovation Solution
A multi-stage serializer circuitry/logic is introduced, comprising SDR, DDR, and QDR stages, utilizing phase locked loop (PLL) clock signals and clock doubling circuits to convert parallel data into high-speed serial data bursts, enhancing the serialization process to support higher IO data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional serialization techniques are used, then device complexity is low, but IO data rate cannot meet requirements above 10 Gbps
Solution Approach 1:
The patent divides the serialization process into multiple stages: a first serializer stage that performs initial parallel-to-serial conversion, and a second serializer stage that further serializes the output. This multi-stage segmentation allows achieving >10 Gbps data rates by breaking down the complex serialization task into manageable stages, each operating at lower individual speeds but combining to achieve the required overall throughput.
Solution Approach 2:
The patent introduces a temporal dimension by using multiple clock domains and phase-locked loops (PLLs) to coordinate the multi-stage serialization process. Different serializer stages operate on different clock phases, effectively adding a time-based dimension to the serialization architecture, which enables higher aggregate data rates while managing complexity through synchronized multi-phase operation.
2Productivity
If multi-stage serializer is implemented to increase IO data rate, then data rate exceeds 10 Gbps, but device complexity increases
Solution Approach 1:
The patent merges multiple serializer stages into a unified multi-stage serialization architecture where the output of one stage feeds directly into the next. By combining these stages and using shared clocking infrastructure (PLLs) to synchronize them, the system achieves high serialization throughput (>10 Gbps) while managing the inherent complexity through integrated design rather than separate independent units.
Solution Approach 2:
The patent changes the operational parameters of the serializer by introducing multiple clock domains with different phases and frequencies. Each serializer stage operates with specific clock parameters managed by PLLs, allowing the system to achieve higher aggregate throughput by coordinating multiple stages with optimized timing parameters rather than relying on a single high-speed serializer.
3Speed
If clock doubling circuits and PLLs are used to manage timing, then serialization speed increases, but power consumption increases
Solution Approach 1:
The patent employs periodic clocking through phase-locked loops (PLLs) that generate synchronized clock signals for multiple serializer stages. By using periodic, phased clocking rather than continuous high-speed operation across all stages simultaneously, the system achieves high serialization speed while allowing certain stages to operate in a more energy-efficient periodic manner, reducing overall power consumption compared to sustained maximum-speed operation.
Data Source
AI summary
An integrated circuit includes first and second double data rate (DDR) shift registers. A multiplexor outputs a serialized data burst by selecting between a first output stream of the first DDR shift register and a second output stream of the second DDR shift register based upon a received selector signal. The selector signal is derived from clock doubling circuitry that provides a frequency that is twice a frequency of a first clock driving the first DDR shift register.