DDR Serializer Architecture for Odd Gearing Ratios
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Solution Overview
Problem
Traditional serializers in FPGAs require costly rate-conversion logic to achieve odd gearing ratios, leading to high silicon cost and power consumption.
Innovation Solution
The implementation of double data rate (DDR) sampling, which uses both rising and falling edges of sampling clocks to achieve odd gearing ratios without the need for additional rate-conversion logic, by configuring serializers to operate with relatively slow clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional SDR sampling with rate-conversion logic is used to achieve odd gearing ratios, then the serializer can process data at the required rate, but silicon cost and power consumption increase significantly
Solution Approach 1:
The patent changes the sampling clock parameter from single-edge triggering (SDR) to double-edge triggering (DDR), allowing the serializer to achieve odd gearing ratios without additional rate-conversion logic. This parameter change in the clock sampling method enables the same data processing rate to be achieved with simpler, lower-cost hardware.
2Device complexity
If DDR sampling is used to achieve odd gearing ratios, then silicon cost and power consumption are reduced, but the clock signal timing becomes more critical
Solution Approach 1:
The patent introduces preliminary setup and hold time constraints for the clock signals to ensure proper sampling at both rising and falling edges. By establishing these timing parameters in advance, the design ensures that data is stable and ready for sampling before each clock edge, thereby managing the increased timing criticality without requiring overly complex timing control circuitry.
3Adaptability or versatility
If a configurable serializer with N-1 and N+1 modes is implemented, then flexibility to handle different word sizes is improved, but the device complexity increases
Solution Approach 1:
The patent implements dynamic configurability where the serializer can switch between N-1 and N+1 operating modes based on the required word size. This dynamic adaptation allows the same hardware structure to handle different gearing ratios (such as 7:1, 9:1) by reconfiguring the parallel-to-serial conversion process, providing versatility without requiring completely separate hardware for each configuration.
Data Source
AI summary
In certain embodiments of the invention, a serializer has (a) an initial, transfer stage that transfers incoming parallel data from a relatively slow timing domain to a relatively fast timing domain and (b) a final, serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that (i) buffers data between the initial and final stages and (ii) can be used to toggle the serializer between an N−1 operating mode (that serializes (N−1) bits of parallel data) and an N+1 operating mode (that serializes (N+1) bits of parallel data) to achieve a net N:1 gearing ratio where N is an odd integer. The serializer can be configurable to support other gearing ratios as well.