DDR Memory Strobe Timing for Higher Bandwidth I/O
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Solution Overview
Problem
Early synchronous memory devices, such as SDR, are insufficient to meet modern speed requirements, and there is a need for a solution that can achieve higher bandwidth without increasing clock frequency.
Innovation Solution
A semiconductor device that generates a stable toggling strobe signal by shifting latency signals in synchronization with a clock to produce internal clocks of different phases, which are used to create a strobe signal for synchronizing data input/output operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock frequency is increased to achieve higher data input/output speed, then processing speed is improved, but power consumption and signal integrity deteriorate
Solution Approach 1:
The patent employs periodic toggling of the strobe signal at half the clock frequency, alternating between high and low states to enable data capture on both rising and falling edges. This periodic action allows double data rate (DDR) operation, achieving doubled bandwidth without increasing clock frequency, thereby avoiding the power consumption and signal integrity issues associated with higher frequency clocks
Solution Approach 2:
The patent segments the data transfer process into two distinct phases within each clock cycle: one phase captures data on the rising edge of the clock, and the other phase captures data on the falling edge. This segmentation is achieved through the toggling strobe signal that operates at half the clock frequency, allowing independent optimization of each phase without increasing overall clock frequency
2Speed
If clock frequency is increased to achieve higher data input/output speed, then processing speed is improved, but signal stability deteriorates
Solution Approach 1:
The strobe signal toggles periodically at half the clock frequency, creating stable and predictable timing windows for data capture. This periodic toggling ensures that data sampling occurs at consistent intervals on both rising and falling edges of the clock, maintaining signal stability while achieving higher effective data transfer rates
Solution Approach 2:
The strobe signal acts as an intermediary between the clock signal and the data capture process. By introducing this intermediate toggling signal that operates at half the clock frequency, the patent decouples the data sampling timing from direct clock edge dependence, thereby improving signal stability and reducing timing skew while maintaining high-speed operation
3Ease of operation
If single data rate operation is used to simplify device operation, then ease of operation is improved, but bandwidth is limited
Solution Approach 1:
The patent segments the data transfer capability into two independent channels: one channel captures data on rising clock edges while the other captures data on falling clock edges. This segmentation is controlled by the toggling strobe signal that alternates between high and low states, effectively creating two parallel data paths within a single differential pair, thereby doubling bandwidth while maintaining operational simplicity
Solution Approach 2:
The single differential signal pair is made multi-functional by enabling it to carry data in both directions (rising edge and falling edge) within each clock cycle. The toggling strobe signal coordinates this dual-function operation, allowing the same physical interface to achieve double the bandwidth of traditional SDR without requiring additional signal pairs or complex operation modes
Data Source
AI summary
A semiconductor device includes an input/output control circuit configured to generate a first driving signal and a second driving signal by shifting a latency signal in synchronization with a clock, and generating a strobe signal which toggles according to logic levels of the first driving signal and the second driving signal; and a data input/output circuit configured to latch input data in synchronization with the strobe signal, and outputting the latched input data as output data.