DDR Deserializer Strobe Training for Asymmetric Data Windows
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Solution Overview
Problem
Double Data Rate (DDR) memory interfaces face challenges in optimizing strobe placement within unequal data-valid windows, leading to jitter and reduced signal integrity, which affects data bandwidth and system performance.
Innovation Solution
A 1-to-2 memory interface deserializer circuit that independently adjusts even and odd strobe signals using adjustable delay lines to optimize their placement within respective data windows, allowing for flexible optimization of timing margins and bit error rates without requiring identical delay specifications for even and odd bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single delay specification is used for both even and odd strobe signals, then the device complexity is reduced, but the jitter and signal integrity deteriorate due to asymmetric strobe placement in unequal data windows
Solution Approach 1:
The patent divides the single delay control into separate delay controls for even and odd strobe signals. The even strobe has its own delay line and control mechanism, while the odd strobe has a separate delay line and control mechanism. This segmentation allows independent optimization of each strobe's timing to match the asymmetric data window requirements, reducing jitter and improving signal integrity without requiring a complex unified control system.
Solution Approach 2:
The patent applies different delay characteristics to different parts of the strobe signal - even strobes receive one delay configuration while odd strobes receive another. This local quality approach recognizes that different portions of the data stream (even vs odd bits) have different timing requirements within the data window, and optimizes each locally rather than applying a global delay setting.
2Reliability
If independent delay lines are provided for even and odd strobe signals, then the jitter and signal integrity are improved, but the device complexity and resource consumption increase
Solution Approach 1:
The patent implements dynamic delay adjustment where the delay lines for even and odd strobes can be independently programmed and adjusted based on measured timing characteristics. This dynamic capability allows the system to adapt to different operating conditions and optimize performance without requiring permanently complex hardware for all possible delay configurations.
Solution Approach 2:
The patent changes the delay parameter independently for even and odd strobe signals based on measured timing margins and jitter characteristics. By allowing the delay parameter to vary between even and odd strobes rather than being fixed, the system achieves better jitter reduction while using a flexible parameter-based approach rather than hardwired complex circuitry.
3Productivity
If asymmetric delay specifications are used for even and odd bits, then the data bandwidth and timing margins are optimized, but the ease of manufacture and design standardization become more difficult
Solution Approach 1:
The patent performs preliminary training and measurement of the even and odd data windows to determine the optimal delay settings before normal operation. This preliminary action characterizes the timing requirements and stores the optimal delay values, allowing the manufacturing process to use standardized components while achieving asymmetric optimization through pre-determined parameter settings rather than custom-designed asymmetric circuitry.
Data Source
AI summary
Methods and apparatus relate to a 1-to-2 memory interface deserializer circuit that, in a training mode, independently positions even and odd strobes in respective even and odd data windows. In an illustrative example, the deserializer circuit may receive a data signal that encodes even and odd data streams on the rising (even) and falling (odd) edges of a strobe clock signal. During a training mode, the deserializer circuit may independently determine, for example, an optimal temporal delay for each of the even strobe and the odd strobe. Adjustable delay lines dedicated to each of the even and odd strobe signals may simultaneously detect valid data window edges to permit determination of a desired delay to optimally position the strobe signals. Various embodiments may advantageously reduce jitter associated with asymmetric strobe and/or data signals to achieve a predetermined specification (e.g., timing margins) within the corresponding data windows.