DDR Subsystem Power Reduction via Cache Hit Rate Feedback
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Solution Overview
Problem
Existing systems for reducing DDR subsystem power consumption in portable computing devices are sub-optimal due to conservative open-loop adjustments that compromise performance and end-user experience, as they operate at worst-case voltage and frequency to handle unpredictable memory traffic patterns.
Innovation Solution
The system integrates a DDR subsystem with a local resource manager that adjusts clock frequency and voltage based on performance requirements from memory clients and cache hit rates, using a system cache and prefetch policies to optimize DDR traffic and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DDR subsystem operates at worst-case voltage and frequency to handle unpredictable traffic, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage and frequency adjustment of the DDR subsystem based on real-time cache performance monitoring. The resource manager continuously monitors cache hit rates and adjusts DDR operating parameters dynamically, transitioning from static worst-case operation to adaptive operation that matches actual system needs.
Solution Approach 2:
The system establishes a feedback loop where the resource manager monitors cache hit rates and uses this information to adjust DDR subsystem parameters. This closed-loop control enables the system to respond to actual performance conditions rather than operating at fixed worst-case settings throughout.
2Use of energy by moving object
If open-loop adjustment of DDR clock frequency is used to conserve power, then power consumption is reduced, but performance drops
Solution Approach 1:
The patent replaces open-loop frequency adjustment with closed-loop control that monitors cache hit rates and adjusts DDR parameters accordingly. This feedback mechanism ensures performance requirements are met while achieving power savings, eliminating the performance drop issue of conservative open-loop adjustments.
Solution Approach 2:
The resource manager autonomously monitors system performance and adjusts DDR parameters without external intervention. The system self-regulates by detecting cache performance metrics and automatically optimizing DDR operating conditions to balance power consumption and performance.
3Use of energy by moving object
If a system cache is incorporated to reduce DDR traffic, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent divides the memory hierarchy into distinct segments: system cache for frequently accessed data and DRAM for bulk storage. This segmentation allows the DDR subsystem to operate at lower frequencies and voltages since not all accesses require full DRAM bandwidth, reducing overall power consumption while maintaining manageable complexity through clear functional separation.
Data Source
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AI summary
Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.