DDR Data I/O Timing Control Using DLL Phase Comparison
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Solution Overview
Problem
Semiconductor devices face challenges in minimizing timing margin loss due to timing skew and variations in access time and propagation delay, especially in DDR synchronous DRAM devices operating with clock signals, which affect their integration density and operation speed.
Innovation Solution
The semiconductor device incorporates a phase comparison circuit, output enablement signal generation circuit, and data input/output circuit, utilizing delay locked loop and phase locked loop circuits to synchronize clock signals and generate pre-control signals, which are used to control the pipe latch circuit, ensuring accurate data input/output operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DDR synchronous DRAM devices operate with clock signals to increase operation speed, then operation speed is improved, but timing margin loss occurs due to timing skew and propagation delay variations
Solution Approach 1:
The patent applies preliminary action by generating pre-control signals in advance before the main data input/output operations. The first pre-control signal is generated from the input clock signal in synchronization with the internal clock signal, and the second pre-control signal is generated by delaying the first pre-control signal. This advance preparation of control signals ensures that timing margins are maintained even at high operating speeds, as the signals are ready before the critical data operations occur.
Solution Approach 2:
The patent uses intermediary elements (delay circuits and phase comparison circuits) to mediate between the clock signals and the data input/output operations. These intermediary circuits introduce controlled delays and phase adjustments to synchronize signals properly, thereby maintaining timing margins while allowing high-speed operation. The delay locked loop (DLL) circuit acts as an intermediary to generate clock signals with adjusted phases to compensate for timing skews.
2Measurement precision
If delay locked loop and phase locked loop circuits are used to synchronize clock signals, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the clock signal generation and control functions into distinct modular circuits: a phase comparison circuit that compares phases, delay locked loop circuits that generate delayed clock signals, and separate pre-control signal generation circuits. This segmentation allows each module to be optimized independently for timing accuracy while managing overall complexity through modular design, making the system more maintainable and easier to adjust.
3Reliability
If pre-control signals are generated with delay times set according to phase information, then timing margin loss is minimized, but signal path complexity increases
Solution Approach 1:
The patent dynamically adjusts the delay times of pre-control signals based on phase information obtained from phase comparison circuits. By changing the delay parameter according to the measured phase difference between clock signals, the system compensates for timing skews and PVT variations, thereby minimizing timing margin loss while maintaining a relatively simple signal path structure through parameter adjustment rather than structural complexity.
Data Source
AI summary
A semiconductor device includes a phase comparison circuit, an output enablement signal generation circuit, and a data input/output (I/O) circuit. The phase comparison circuit compares a phase of a clock signal with a phase of a delay locked loop (DLL) clock signal to generate a phase information signal. The output enablement signal generation circuit latches an internal command in response to a first pre-control signal and outputs the latched internal command as an output enablement signal in response to an operation clock signal and a second pre-control signal. The output enablement signal generation circuit generates the first pre-control signal according to an internal clock signal and an input clock signal. The data I/O circuit receives input data and output the received input data as output data synchronized with a strobe signal in response to the output enablement signal.