DDR Internal Write Leveling Across Voltage Domains
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Solution Overview
Problem
Existing internal write leveling (IWL) calibration methods in memory devices suffer from inaccuracies due to operating in different voltage domains and limited gating accuracy, leading to obscured signal capture errors and synchronization failures during write operations.
Innovation Solution
Implementing multiple IWL circuits in different voltage domains, one for internal write leveling and another for normal operations, combined through a combining circuit to achieve accurate synchronization by evaluating the timing relationship between data strobe signals and write command signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single IWL circuit operates in a different voltage domain for calibration, then the calibration process can be completed, but synchronization accuracy deteriorates due to voltage domain mismatches and gating logic limitations
Solution Approach 1:
The patent divides the IWL evaluation into two separate circuits: a first IWL circuit operating in a first voltage domain for calibration, and a second IWL circuit operating in a second voltage domain for accurate timing evaluation. This segmentation allows each circuit to operate in its optimal voltage domain, resolving the contradiction between calibration completion and synchronization accuracy.
Solution Approach 2:
The patent introduces a voltage domain conversion mechanism that acts as an intermediary between the first voltage domain (calibration) and the second voltage domain (operation). This intermediary enables accurate timing relationship evaluation by translating signals between voltage domains, thereby maintaining synchronization accuracy while preserving the calibration capability.
2Ease of operation
If gating logic is used to capture data strobe signal pulses, then the IWL calibration can proceed, but measurement accuracy deteriorates due to obscured signal capture errors
Solution Approach 1:
The patent introduces a pulse capture circuit that acts as an intermediary between the data strobe signal and the IWL evaluation logic. This intermediary circuit captures pulses without the limitations of traditional gating logic, eliminating obscured signal capture errors while maintaining calibration execution capability.
Solution Approach 2:
The patent replaces the traditional gating logic mechanism with a more advanced pulse capture circuit that uses different operational principles. This substitution eliminates the inherent limitations of gating logic (such as obscured errors) while preserving the ability to execute IWL calibration.
3Measurement precision
If IWL calibration is performed in the same voltage domain as write operations, then timing evaluation can be accurate, but reliability deteriorates due to decision boundary errors
Solution Approach 1:
The patent segments the operational domains: the first IWL circuit operates in a first voltage domain for calibration with accurate timing evaluation, while the second IWL circuit operates in a second voltage domain for reliable write operations. This segmentation prevents decision boundary errors from affecting write operation reliability while maintaining timing evaluation accuracy.
Solution Approach 2:
The patent applies different operational characteristics to different parts of the system: the first voltage domain is optimized for timing evaluation with relaxed decision boundaries, while the second voltage domain is optimized for reliable write operations with strict decision boundaries. This local quality differentiation resolves the contradiction between timing accuracy and operational reliability.
Data Source
AI summary
A memory device includes a first internal write leveling (IWL) circuit configured to evaluate a timing relationship between a pair of data strobe signals and a write command signal according to a first IWL scheme, and generate a first IWL result signal indicating whether the timing relationship satisfies a first IWL condition; a second IWL circuit configured to evaluate the timing relationship between the pair of data strobe signals and the write command signal according to a second IWL scheme, and generate a second IWL result signal indicating whether the timing relationship satisfies a second IWL condition, wherein the second IWL scheme is different from the first IWL scheme; and a combining circuit configured to receive the first IWL result signal and the second IWL result signal, and generate a final IWL result signal indicating whether the timing relationship satisfies both the first IWL condition and the second IWL condition.