DDR-2 Memory Data Resynchronization Circuit
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Solution Overview
Problem
DDR-2 DRAM memory devices introduce delays that complicate synchronous data transfer due to unpredictable timing relationships between DQS/DQSN clock signals and the system clock, especially under variations in process, voltage, and temperature, making direct data transfer to systems with different clock frequencies challenging.
Innovation Solution
A method is implemented to generate a data valid strobe signal synchronous with the system clock by detecting sequential transitions of DQS or DQSN signals from DDR-2 compliant memory devices, extending the data valid window through a two-stage data capture process, and using enable signals to synchronize data transfer between the DDR-2 clock domain and the system clock domain without an intervening clock domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer occurs at high frequency (200-333 MHz), then productivity increases, but timing predictability deteriorates due to delays becoming comparable with clock period
Solution Approach 1:
The patent introduces DQS/DQSN signals as intermediary clock signals that are delayed versions of the system clock, specifically timed to account for data path delays. These intermediary signals serve as the actual clocking mechanism for data capture, decoupling the timing requirements from the system clock and making the system robust against delay variations.
Solution Approach 2:
The system performs preliminary timing adjustment by delaying the clock signal to create DQS/DQSN that are already compensated for the expected data path delays. This preliminary action ensures that when data arrives after traversing the data path, the timing relationship remains predictable and reliable.
2Reliability
If additional resynchronization stage is added, then timing reliability improves, but device complexity increases
Solution Approach 1:
The patent makes the existing DQS/DQSN signals serve multiple functions: they act as clock signals for data capture, provide timing reference for resynchronization, and enable extended data valid window. This multi-functionality achieves reliable data capture without adding separate dedicated resynchronization circuitry.
Solution Approach 2:
The system uses its own delayed clock signals (DQS/DQSN) that are already generated for data path compensation to also perform the resynchronization function. The same signals that compensate for data path delays are reused to clock the data capture registers, eliminating the need for separate resynchronization clock sources.
Data Source
AI summary
The reliable capture of data from a DDR-2 memory device can be provided using timing signals provided by the DDR-2 memory device in conjunction with enable signals generated there from. The reliable capture of data from the DDR-2 DRAM can be used to extend the data valid window for which the captured data is provided to a system that is in communication with the memory controller. Extending the data valid window can enable the generation of a data valid strobe signal (that is synchronous with a system clock used to operate the system), which satisfies all timing requirements associated with interfacing the DDR-2 memory device to the system over a wide variation of process, voltage, and temperature.