DDR3 FPGA Read Leveling With Delay Calibration
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Solution Overview
Problem
The increasing data transfer rates between memory devices and FPGAs outpace the memory devices' capacity, leading to data recovery errors due to suboptimal timing between phase-shifted DQS signals and system clocks in DDR3 memory interface standards, which conventional techniques like first-in-first-out memories fail to adequately address.
Innovation Solution
Implementing leveling elements, such as delay elements or intermediate registers, between input and output registers to calibrate and adjust the delay of input signals, ensuring error-free data transfer by averaging minimum and maximum delays for optimal phase alignment of DQS and DQ signals with the system clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques like first-in-first-out memories are used to retiming signals, then data transfer between memory devices and FPGA is enabled, but the circuit size and complexity increase significantly
Solution Approach 1:
The patent extracts the essential retiming function from complex FIFO memory circuits and implements it using simple delay elements and phase-shifted clocks. By taking out only the necessary timing adjustment capability, the solution achieves reliable data transfer without the bulk and complexity of conventional FIFO implementations.
Solution Approach 2:
The patent changes the timing parameters of the clock signal by introducing phase-shifted versions of the system clock. By adjusting the phase relationship between clocks and data signals through delay elements, the patent achieves proper synchronization without requiring complex memory-based retiming circuits.
2Stability of the object's composition
If the system clock is routed using fly-by topology to memory devices, then signal integrity is improved, but the DQ and DQS signals become asynchronous with the system clock
Solution Approach 1:
The patent applies preliminary phase adjustment to the clock signals before they are used to sample the asynchronous DQ and DQS signals. By pre-shifting the clock phases to account for the fly-by topology delays, the patent ensures that data sampling occurs at optimal timing points, preventing recovery errors before they can occur.
Solution Approach 2:
The patent introduces phase-shifted clock signals as intermediary timing references between the fly-by routed system clock and the data sampling operations. These intermediary clocks act as mediators that bridge the timing gap created by the fly-by topology, enabling reliable data recovery despite the asynchronous nature of the signals.
3Productivity
If data is transferred at high speeds between memory devices and FPGA, then data throughput is improved, but timing errors and data recovery errors increase
Solution Approach 1:
The patent implements dynamic timing adjustment by using multiple phase-shifted clock signals that can be selectively applied based on the actual timing requirements of each data group. This dynamic approach allows the system to adapt to varying timing conditions at high speeds, maintaining data recovery accuracy while maximizing throughput.
Solution Approach 2:
The patent uses periodic phase-shifted clock signals to sample data at multiple timing points throughout each clock cycle. By periodically sampling data with different phase offsets, the system can reliably capture high-speed data transitions regardless of their exact timing, thereby maintaining data recovery accuracy at increased throughput rates.
Data Source
AI summary
Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.