DDR4 Memory Buffer Circuits for High-Speed Error-Checked Data Transfer
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Solution Overview
Problem
The high error rate of data read/write operations in DDR4 memory chips poses a challenge in effectively managing data transfer, particularly in ensuring data integrity and efficiency across multiple memory chips.
Innovation Solution
A write circuit and read circuit are designed to collect, check, and adjust data using conversion control data, allowing for accurate data transfer between memory chips, with a memory buffer and module configuration that utilizes these circuits to manage data integrity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written into or read from DDR4 memory chips at high frequency, then productivity is improved, but the error rate increases
Solution Approach 1:
The patent applies preliminary action by performing data checking and conversion control before data is written into or read from the memory chips. The write circuit includes a check unit that verifies data integrity before writing, and the read circuit includes a check unit that verifies data after reading. This preliminary verification prevents error propagation and ensures data reliability even at high transfer speeds.
Solution Approach 2:
The patent implements feedback mechanisms through conversion control data that is generated based on the state of data being transferred. The write circuit generates conversion control data based on write data, and the read circuit generates conversion control data based on read data. This feedback loop allows the system to dynamically adjust data conversion and checking operations to maintain reliability at high speeds.
2Reliability
If data checking and conversion control operations are performed, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing check units and conversion control data generating units that serve multiple functions. These units perform both data verification and conversion control operations, eliminating the need for separate dedicated circuits for each function. This multi-functionality reduces overall circuit complexity while maintaining comprehensive data reliability checks.
Solution Approach 2:
The patent merges the data checking function and conversion control function into integrated circuit units. The check unit and conversion control data generating unit are combined within the same circuit architecture, allowing simultaneous execution of verification and conversion operations. This merging reduces the number of separate components and simplifies the overall device structure.
3Quantity of substance
If multiple memory chips are used to increase capacity, then quantity of substance is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory system into multiple independent memory chips (first memory chip and second memory chip). Each chip can be independently managed and operated, allowing the system to scale capacity by adding more chips without proportionally increasing complexity. The write unit and read unit handle multiple chips through standardized interfaces.
Solution Approach 2:
The write unit and read unit are designed with multi-functionality to handle data operations across multiple memory chips. These units can selectively write to or read from different chips based on conversion control data, providing a unified interface that manages complex multi-chip operations without requiring separate control circuits for each chip.
Data Source
AI summary
The present invention provides a write circuit, a read circuit, a memory buffer and a memory module. The write circuit includes: a data collecting unit, a first check unit, a data restoring unit, a first check data generating unit, a first adjusting unit and a write unit; the read circuit includes: a data read unit, a second check unit, an output data generating unit, a second check data generating unit, a second adjusting unit and an output unit; the memory buffer includes the write circuit and the read circuit; the memory module includes the memory buffer and multiple memory chips connected to the memory buffer.