DDR4 Memory Data Bus Inversion Control for Low Power Transmission
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Solution Overview
Problem
The high working frequency of DDR4 memory chips increases the error rate of data read/write operations, necessitating an effective solution to manage data transmission efficiently while minimizing power consumption.
Innovation Solution
A data read/write system that employs a check data generation unit, data processing units, and data output/write units to generate and manage check data and inversion control data, using data bus inversion control lines to optimize data transmission, specifically for DDR4 X4 memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the working frequency of DDR4 memory chip is increased, then the memory capacity and processing speed are improved, but the error rate of data read/write operations is greatly increased
Solution Approach 1:
The patent applies preliminary action by generating check data before the actual data transmission. The check data generation unit creates verification data based on the data to be transmitted, and this check data is transmitted along with the actual data. The receiving end then uses this pre-generated check data to verify the integrity of the received data, thereby preventing errors before they affect system operation.
Solution Approach 2:
The patent implements feedback through the check data verification mechanism. The receiving end compares the received data with the transmitted check data to detect any errors. This feedback loop allows the system to identify and correct data transmission errors, maintaining reliability even at high working frequencies where errors are more likely to occur.
2Quantity of substance
If data transmission is performed at high frequency, then the memory capacity is increased, but the power consumption of interface data transmission is increased
Solution Approach 1:
The patent extracts the essential verification function from the data transmission process by separating check data generation from the main data stream. The check data generation unit operates independently and only processes the data that needs to be transmitted, reducing unnecessary computational overhead and power consumption while maintaining verification capabilities.
Solution Approach 2:
The patent changes the parameter of data transmission by introducing inversion control data that modifies the data values based on specific conditions. This allows the system to optimize power consumption by adjusting data transmission parameters dynamically, reducing energy usage during verification processes while maintaining high memory capacity.
3Reliability
If check data and inversion control data are added to data transmission, then the data reliability is improved, but the device complexity is increased
Solution Approach 1:
The patent applies universality by designing the check data generation unit and data processing units to perform multiple functions. The same circuitry used for data processing also generates check data and processes inversion control data, reducing the need for separate dedicated circuits and thereby limiting the increase in device complexity while improving reliability.
Solution Approach 2:
The patent merges the check data generation function with the existing data processing units. Instead of adding completely separate verification circuits, the system integrates check data generation into the data processing flow, combining multiple functions into unified circuit blocks that reduce overall device complexity.
Data Source
AI summary
The present invention provides a data read/write system. The data read/write system includes a memory controller and a memory module. The memory controller includes a first control circuit, a data output circuit, and a data receiving circuit. The memory module includes a memory buffer and at least two memory chips. The memory buffer includes a second control circuit, a write circuit, and a read circuit. The advantage of the present invention is that, when data is read or written into the memory chip, especially a DDR4 X4 memory chip, low power consumption of interface data transmission can be achieved through a data bus inversion control line DBI.