Nested Mode Register Architecture for DDR4 Readback Access
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Solution Overview
Problem
Existing memory devices, such as those compliant with the DDR4 standard, lack a method to directly read back data stored in mode registers, requiring extensive tuning and calibration for effective operation, and have limited functionality due to a predefined number of mode registers.
Innovation Solution
A nested mode register architecture is introduced, allowing access to additional mode registers using the standard DDR4/LPDDR4 command protocol, enabling read operations and expanding functionality without departing from standard specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If mode registers are implemented according to traditional standards (DDR4), then the device complies with standard specifications, but the device lacks the ability to directly read back mode register data and requires extensive tuning/calibration
Solution Approach 1:
The mode register is configured to perform multiple functions: it can be written to using the standard mode register set command and also read back using the multipurpose register function. This dual functionality eliminates the need for separate read mechanisms while maintaining standard compliance.
Solution Approach 2:
The multipurpose register function serves as an intermediary mechanism that enables read access to mode register data. By configuring the mode register to also function as a multipurpose register, the system can read back mode register contents without requiring a dedicated read path.
2Adaptability or versatility
If additional mode registers are implemented beyond the predefined number, then functionality is expanded, but the device departs from standard specifications
Solution Approach 1:
The multipurpose register function, already present in the device for other purposes, is configured to provide read access to mode register data. This existing structure is repurposed to support additional functionality without adding new standard-noncompliant components.
Solution Approach 2:
The mode register system uses its own existing multipurpose register capability to provide read access to itself. The device leverages its own internal resources to achieve the desired functionality rather than requiring external additions that would violate standard specifications.
3Quantity of substance
If mode registers store limited bits (e.g., 14 bits) as defined by standards, then standard compliance is maintained, but the amount of storable control information is restricted
Solution Approach 1:
Multiple mode registers are nested within the addressable range, with each register providing additional control settings. The first mode register at a given address contains control data, and subsequent mode registers at adjacent addresses provide additional settings, creating a nested structure of expandable functionality.
Solution Approach 2:
The system expands from a single mode register to multiple mode registers along the address dimension. By addressing mode registers at consecutive addresses (e.g., address, address+1, address+2), the system effectively adds an address dimension to the mode register space, enabling storage of additional control information while maintaining the standard 14-bit width of each individual register.
Data Source
AI summary
Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.