Automated Test Code Generation for DDR4 Memory Verification
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Solution Overview
Problem
The existing chip testing methods require substantial manpower and resources due to the need for manually written big-data test codes, which limits the efficiency of memory testing, especially for high-speed and high-capacity memory chips.
Innovation Solution
A method and device that automatically generate test codes by determining language rules, product specifications, and timing specifications to select and generate test patterns, enabling the automatic testing of memory chips using a high-speed test machine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual code writing is used for chip testing, then testing can be performed with simple equipment, but testing efficiency is low and substantial manpower resources are required
Solution Approach 1:
The system enables automatic generation of test codes through self-service mechanisms. The test code generation module automatically creates test codes based on chip specifications and test requirements, eliminating the need for manual code writing by testers. This automation directly addresses the contradiction by improving productivity while managing code complexity through systematic generation processes.
Solution Approach 2:
The patent replaces the mechanical process of manual code writing with an automated computer-based system. The test code generation module substitutes human testers' manual efforts with algorithmic generation, thereby improving testing efficiency and reducing the substantial manpower resources previously required while systematically handling code complexity.
2Speed
If manually-written test codes are used, then flexibility in handling different chip models is maintained, but testing speed and efficiency are limited
Solution Approach 1:
The system performs preliminary action by pre-establishing a comprehensive library of test patterns covering various chip models and testing scenarios. When a specific chip needs testing, the appropriate test patterns are automatically selected and generated from this pre-prepared library, eliminating the time-consuming process of writing codes from scratch and significantly improving testing speed.
Solution Approach 2:
The patent utilizes parameter changes to adapt test patterns to different chip models. By modifying parameters such as chip capacity, speed grade, and architectural features, the system generates customized test codes automatically. This approach maintains flexibility for different chip models while dramatically reducing the time required compared to manual code writing.
3Reliability
If comprehensive test coverage is achieved for high-speed high-capacity memories, then reliability is improved, but code volume increases and manual writing becomes impractical
Solution Approach 1:
The patent segments comprehensive test coverage into modular test patterns, each targeting specific functional aspects or reliability criteria of high-speed high-capacity memories. These segmented test patterns can be independently selected, combined, and automatically generated based on the specific chip being tested. This segmentation maintains thorough reliability testing while making the code volume manageable through systematic organization and automated generation.
Data Source
AI summary
A chip testing method, device, electronic apparatus, and computer readable medium are provided, relating to the field of chip testing. The method includes: determining a language rule of a chip to be tested; determining product and timing specifications of the chip to be tested; selecting a test pattern from a test pattern library according to the language rule and the product and timing specifications; generating a test code according to the product and timing specifications and the test pattern; and automatically testing the chip to be tested by using the test code. The chip testing method, device, electronic apparatus and computer readable medium can automatically generate a big-data test code for complex memories, and rapidly generate, in a standardized way, test codes for DDR4 memories of different specifications, thereby improving the efficiency of chip product verification analysis.