DDR5 and CXL Memory Interleaving for Unified Bandwidth Access
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Solution Overview
Problem
Existing computing systems face challenges in efficiently utilizing the full memory bandwidth of heterogeneous memory targets due to tiered memory approaches that separate memory resources into distinct address ranges, limiting applications from exploiting the additional bandwidth offered by different memory types and placing a burden on the operating system or virtual machine manager to schedule applications based on their bandwidth needs.
Innovation Solution
The method involves interleaving heterogeneous memory targets, such as DDR5 and CXL memory, into a single continuous software-visible address range, allowing applications to access the full memory bandwidth by configuring these targets through system BIOS and exposing them to the operating system or virtual machine manager, thereby simplifying scheduling and enabling uniform application distribution across the address range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If memory resources are separated into distinct address ranges for different memory types, then each memory type can be managed independently, but applications cannot exploit the additional bandwidth offered by different memory types and the operating system must schedule applications based on their bandwidth needs
Solution Approach 1:
The patent merges multiple heterogeneous memory targets (DDR5, CXL, HBM) into a unified address space, allowing applications to access all memory types through a single continuous address range. This eliminates the need for separate address ranges and OS scheduling, while enabling applications to automatically exploit the combined bandwidth of all memory types through uniform access patterns.
2Productivity
If heterogeneous memory targets are interleaved into a single continuous address range, then applications can access full memory bandwidth, but the system must handle address mapping and routing complexity
Solution Approach 1:
The patent introduces an intermediary address translation layer (through the memory management unit and routing logic) that handles the complexity of mapping virtual addresses to physical addresses across heterogeneous memory targets. This intermediary absorbs the routing complexity, allowing applications to use simple uniform access while the system manages the sophisticated address mapping and memory target selection in the background.
3Productivity
If multiple memory targets are interleaved to improve parallelism, then memory throughput increases, but memory access latency may increase due to distributed access patterns
Solution Approach 1:
The patent segments the unified address space into interleaved portions that map to different memory targets, allowing simultaneous access to multiple memory devices. By distributing memory accesses across multiple targets in parallel, the system achieves higher aggregate throughput while the segmentation strategy minimizes latency by ensuring that frequently accessed data can be served from any of the interleaved memory targets.
Data Source
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AI summary
An apparatus comprising a first memory interface of a first type to couple to at least one first memory device; a second memory interface of a second type to couple to at least one second memory device; and circuitry to interleave memory requests targeting contiguous memory addresses among the at least one first memory device and the at least one second memory device.