4:1 Multiplexed DDR5 DIMM Ranks for Lower-Power Bandwidth Scaling
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Solution Overview
Problem
Current DDR5 memory systems face challenges with high power consumption and scalability issues due to limited multiplexing capabilities, leading to inefficiencies in bandwidth and power efficiency, especially in BL16 mode.
Innovation Solution
A 4:1 multiplexing configuration for LPDDR5 memory modules that interconnects 4 or 8 ranks through interleaved pseudo channels, operating DRAMs at one-quarter of the full data rate, reducing command and address copies, and utilizing existing DDR5 connectors without modifying pinouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DDR5 memory systems use conventional multiplexing configurations, then bandwidth can be maintained, but power consumption increases and scalability is limited
Solution Approach 1:
The memory system is segmented into four separate pseudo-channels (PC0-PC3), each handling a portion of the data traffic. This segmentation allows the system to distribute power consumption across multiple independent channels while maintaining high aggregate bandwidth. Each pseudo-channel can be independently activated based on access patterns, reducing overall power usage when full bandwidth is not required.
Solution Approach 2:
The patent introduces a new dimension of multiplexing by interleaving data across four pseudo-channels instead of the conventional two-rank configuration. This 4:1 multiplexing ratio represents a dimensional change in the data organization structure, enabling higher bandwidth utilization while improving power efficiency through more granular channel management.
2Adaptability or versatility
If DDR5 memory systems use conventional multiplexing configurations, then existing infrastructure can be maintained, but scalability is limited
Solution Approach 1:
The four pseudo-channels are designed to be universal and interchangeable, allowing the memory system to scale from 4 to 8 ranks while maintaining the same basic architecture. The interleaved pseudo-channel configuration can accommodate different rank configurations without requiring fundamental design changes, enhancing scalability while keeping the multiplexing logic relatively simple through standardized channel interfaces.
3Speed
If DRAMs operate at full data rate, then speed is maximized, but power consumption increases
Solution Approach 1:
The system employs periodic activation of the four pseudo-channels based on memory access patterns. Instead of continuously operating all channels at full speed, the controller periodically activates only the necessary pseudo-channels required for current access operations. This periodic action maintains maximum speed when needed while reducing power consumption during partial utilization scenarios.
Solution Approach 2:
The multiplexing configuration dynamically adjusts which pseudo-channels are active based on real-time memory access requirements. The system can transition between different operational states, activating 1, 2, 3, or all 4 pseudo-channels as needed, thereby optimizing the dynamic balance between speed and power consumption rather than operating at a fixed state.
Data Source
AI summary
Disclosed herein is memory device that includes a printed circuit board (PCB) and a plurality of dynamic random-access memory (DRAM) devices arranged on the PCB and logically divided into four pseudo-channels. A shared command/address (C/A) bus of the device is configured to transmit command signals to all four pseudo-channels and a set of multiplexers on the device are controllable to selectively couple data signals between the four pseudo-channels and a memory controller. A control interface of the device is configured to interleave data burst transactions of the data signals across the four pseudo-channels, wherein a burst of the data burst transactions is distributed across two groups, each group comprising two of the four pseudo-channels operating in parallel.