DDR5 DM Pin Impedance Control via Mode Register Decoding
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Solution Overview
Problem
The Double Data Rate 5 SDRAM (DDR5) specification's Package Output Driver Test Mode (PODTM) is not adapted for the Data Mask (DM) pin, leading to circuit processing errors due to undefined output driver state, which affects impedance testing and reliability.
Innovation Solution
A control method is provided to control the impedance of the DM pin in a preset test mode, using Mode Registers (MRs) to define impedance parameters, avoiding the need for an output driver state definition and related circuits, thereby enabling impedance testing without causing circuit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the Package Output Driver Test Mode (PODTM) from DDR5 specification is applied to the DM pin, then impedance testing capability is improved, but circuit processing errors occur due to undefined output driver state
Solution Approach 1:
The patent applies different impedance control strategies to different pins based on their functional characteristics. The DM pin is identified as a special case that should not follow the general PODTM procedure. Instead, the DM pin is handled with a dedicated impedance control method that respects its write-only nature and avoids undefined output driver states, while other pins can continue to use the standard PODTM approach.
Solution Approach 2:
The patent inverts the conventional approach by not applying PODTM to the DM pin at all, rather than trying to adapt PODTM to work with the DM pin's unique characteristics. The solution involves detecting when the DM pin is selected for impedance testing and switching to an alternative impedance control method that is specifically designed for the DM pin's functional constraints.
2Reliability
If the DM pin is excluded from impedance testing, then circuit processing errors are avoided, but impedance testing completeness deteriorates
Solution Approach 1:
The patent creates a universal impedance testing framework that can handle both standard pins (DQ pins) and the special DM pin through a unified control mechanism. The Mode Register decoding logic provides a universal interface that automatically selects the appropriate impedance control strategy based on the pin type being tested, making the testing system adaptable to different pin configurations without requiring separate testing procedures.
3Measurement precision
If additional circuits are added to support DM pin in PODTM, then impedance testing capability is improved, but device complexity increases
Solution Approach 1:
The patent utilizes existing Mode Register decoding circuits and impedance control mechanisms to handle the DM pin's special requirements. The solution leverages the operational mode register decoding logic that already exists in the memory device, extending its functionality to recognize DM pin test scenarios and automatically apply the appropriate impedance control without requiring separate dedicated circuits for DM pin handling.
Data Source
AI summary
A control method includes: decoding a third Operand (OP) in a third Mode Register (MR) and a fourth OP in a first MR; and in response to the semiconductor memory being in a preset test mode, controlling, in a case where the third OP meets a first decoding condition, the impedance of a Data Mask (DM) pin to be a first value; or controlling, in a case where the third OP meets a second decoding condition, the impedance of the DM pin to be a second value according to the fourth OP; wherein the third OP is configured to indicate whether the DM pin is a test object in the preset test mode, and the fourth OP is configured to indicate whether the DM pin is enabled.