DDR5 Gear Down Clock Path Symmetry
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Solution Overview
Problem
In DDR5 SDRAMs, the gear down mode leads to uneven influences of NBTI and PBTI between clock paths due to the asymmetric supply of divided clock signals.
Innovation Solution
The implementation of a gear down control circuit that adjusts the disable signals to ensure symmetrical operation of clock paths by synchronizing the enable signals with the internal clock signals, thereby maintaining balanced influences of NBTI and PBTI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the divided clock signal is supplied only to one clock path in gear down mode, then the chip selection signal pulse width is extended to two clock cycles, but the influences of NBTI and PBTI become uneven between the two clock paths
Solution Approach 1:
The patent applies asymmetry by intentionally creating different operating conditions for the two clock paths during gear down mode. One clock path receives the divided clock signal while the other does not, allowing each path to be optimized for its specific function. This asymmetric approach resolves the contradiction by accepting uneven NBTI/PBTI influences as a trade-off for achieving the extended pulse width functionality.
Solution Approach 2:
The patent implements dynamic operation by switching between normal mode (both clock paths active) and gear down mode (one clock path active) based on operational requirements. The system dynamically adjusts clock signal distribution to optimize performance for different operational scenarios, extending pulse width when needed while maintaining reliability through mode switching.
2Productivity
If the divided clock signal is supplied only to one clock path, then the gear down mode achieves extended pulse width, but the characteristics of clock paths become inconsistent
Solution Approach 1:
The patent segments the clock path functionality by separating the two clock paths into different operational roles during gear down mode. One path is designated for receiving the divided clock signal while the other path operates differently, allowing each segment to be optimized for its specific purpose. This segmentation enables extended pulse width capability while managing the inconsistency through functional differentiation.
Solution Approach 2:
The patent applies local quality by giving different operational characteristics to different parts of the clock distribution system during gear down mode. The clock path receiving the divided signal has different properties than the path that doesn't receive it, allowing each local region of the system to be optimized for its specific function while maintaining overall system productivity.
Data Source
AI summary
An example apparatus includes a clock divider configured to divide an original clock signal to generate a first clock signal and a second clock signal having different phase from the first clock signal; a first clock path; a second clock path; and a control circuit configured to: in a first operation mode, supply at least one pulse of the first clock signal to the first clock path and at least one pulse of the second clock signal to the second clock path; and in a second operation mode, supply at least one pulse of one of the first and second clock signals to the first clock path and supply at least one pulse of one of the first and second clock signals to the second clock path.