DDR5 DRAM Loopback Phase Switching Circuit
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Solution Overview
Problem
In DDR5 DRAM, the loopback Write Burst Output Mode function faces challenges in accurately selecting and sending back loopback data due to timing differences between the write start signal and the data strobe signal, which can lead to errors in loopback operations.
Innovation Solution
A selection signal generation circuit is introduced to dynamically change the phase of loopback data by using a selection signal INVPH, which is synchronized with the internal data strobe signal and the write start signal, ensuring correct loopback data selection even with timing differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If loopback data is sent back using write data from a previous write operation, then the loopback function can operate, but timing differences between write start signal and data strobe signal cause phase switching errors
Solution Approach 1:
The patent applies preliminary action by generating the selection signal INVPH in advance based on the write start signal WRSRT, and using this pre-generated signal to control the phase switching of loopback data. This ensures that the phase selection is prepared before the actual data transfer occurs, preventing timing-related phase switching errors between the write start signal and data strobe signal.
2Ease of operation
If the phase of loopback data is switched based on write data timing, then data can be selected for loopback, but timing misalignment with data strobe signal causes selection errors
Solution Approach 1:
The patent implements feedback by using the write start signal WRSRT (which reflects the actual timing of write operations) to generate the selection signal INVPH that controls phase switching. This feedback mechanism ensures that the phase selection adapts to the actual timing conditions, maintaining accurate data selection despite variations in timing between write start signal and data strobe signal.
Data Source
AI summary
An example apparatus includes a first circuit configured to receive a plurality of first write data and then a plurality of second write data responsive to a write command; a second circuit configured to select one or ones of the plurality of first write data and one or ones of the plurality of second write data based, at least in part, on a first selection signal and a second selection signal following the first selection signal, respectively; and a third circuit configured to: receive an internal write command signal provided correspondingly to the write command; mask a portion of the internal write command signal a timing of which partially overlaps the plurality of first write data to provide a masked internal write command signal; and provide the second selection signal based, at least in part, on the second internal command signal.