Multi-phase Clock Division for DDR5 SDRAM
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Solution Overview
Problem
In semiconductor devices, particularly DDR5 SDRAM, dividing a fast clock into multiple phases for internal use can result in uncertainty about the starting phase, leading to incorrect bit counting due to variable write preamble lengths and the inability to reset between data bursts, which affects the correct capture and ordering of write data.
Innovation Solution
The implementation of multi-phase generation circuitry and phase detection circuitry that includes delay and selection circuitry to determine the leading phase and adjust bit counting based on programmable preamble lengths, ensuring accurate data capture and handling of variable burst lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fast clock is divided into multiple phases for internal use, then clock frequency performance is improved, but phase uncertainty and bit counting accuracy deteriorate
Solution Approach 1:
The patent implements a reset mechanism that performs preliminary action by resetting the bit count to zero at the beginning of each data burst. This preliminary reset ensures that phase detection and bit counting start from a known state, eliminating cumulative errors that would otherwise accumulate across multiple bursts. The reset is triggered by detecting the start of a new data burst, allowing the system to maintain accuracy despite continuous operation at high clock frequencies.
Solution Approach 2:
The patent employs feedback through phase detection circuitry that continuously monitors which phase receives the first incoming clock edge and uses this information to adjust bit counting. The system feeds back the detected leading phase information to control logic that then correctly interprets subsequent data bursts. This closed-loop feedback mechanism ensures that even when phase relationships shift between bursts, the system can accurately determine bit positions and maintain synchronization.
2Productivity
If bit counting is performed without reset between data bursts, then operational continuity is improved, but bit counting accuracy deteriorates
Solution Approach 1:
The system performs a preliminary reset of the bit count counter at the start of each data burst. This reset action occurs before data reception begins, ensuring that the counter starts from zero for each new burst. The reset is automatically triggered when the system detects the beginning of a data burst, allowing continuous operation without manual intervention while maintaining accurate bit counting for each individual burst.
Solution Approach 2:
The patent implements dynamic control of the bit count reset based on data burst detection. Rather than a static reset mechanism, the system dynamically determines when to reset by monitoring for the arrival of new data bursts. This dynamic approach allows the system to adapt its reset timing to varying operational conditions, maintaining both continuous operation and counting accuracy across multiple bursts with variable lengths.
3Adaptability or versatility
If variable write preamble lengths are supported, then adaptability is improved, but phase synchronization and bit counting accuracy deteriorate
Solution Approach 1:
The system performs preliminary detection of the leading phase at the start of each data burst, before variable preamble lengths can cause synchronization issues. By establishing the correct phase reference early in the burst, the system can then accurately count bits regardless of how many preamble cycles precede the actual data. This preliminary phase establishment acts as a foundation that enables accurate bit counting through subsequent variable-length preambles.
Solution Approach 2:
The patent uses feedback from phase detection circuitry to continuously monitor which phase receives the first clock edge of each data burst. This feedback information is used to adjust bit counting operations in real-time, ensuring that even when preamble lengths vary between bursts, the system can correctly identify the phase boundaries and count bits accurately from the start of each new burst.
Data Source
AI summary
Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.