DDR5 Memory Data Path Power Savings via One-Hot Encoding

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Solution Overview

Problem

DDR5 SDRAM memory devices consume excessive power due to high transitions in data patterns on transmission lines, which is not efficiently managed by existing technologies.

Innovation Solution

Implementing a one-hot data encoding technique that reduces the 16-bit data bus to a phase-separated set of 4 nibbles, each containing a single '1' bit, minimizing transitions and power consumption by using quad pumping parallelizer circuitry and one-hot decoders in the data path architecture.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If conventional data encoding is used on the 16-bit data bus, then data transmission capability is maintained, but power consumption increases due to high transitions in data patterns

Engineering Contradiction:
Improvepower consumptionVSAvoiddata transmission capability
Core Design Contradiction:
Use of energy by stationary objectVSReliability

Solution Approach 1:

The patent changes the encoding parameter from conventional binary to one-hot encoding, where each nibble is represented by a unique one-hot code. This transformation reduces the number of transitions in data patterns, thereby lowering power consumption while maintaining data transmission capability through the modified encoding scheme

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent segments the 16-bit data bus into four separate 4-bit nibble channels, each carrying one-hot encoded data. This segmentation allows independent control and optimization of each nibble's transmission, reducing overall transitions and power consumption while preserving the complete data transmission function

Inventive Principle:
Principle #1Segmentation

2Use of energy by stationary object

If one-hot encoding is applied to reduce transitions, then power consumption decreases, but device complexity increases due to additional encoding circuitry

Engineering Contradiction:
Improvepower consumptionVSAvoidencoding circuitry complexity
Core Design Contradiction:
Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by pre-defining the one-hot encoding mappings for all possible 4-bit nibble values (0-15) before data transmission occurs. This pre-computed encoding scheme eliminates the need for complex real-time encoding logic, reducing circuitry complexity while maintaining the power savings benefits of one-hot encoding

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent makes the encoding circuitry universal by using a standardized one-hot encoding scheme that can be applied to all data transmissions regardless of the specific data pattern. This universal approach simplifies the circuit design compared to custom encoding for each data type, as the same encoding logic handles all possible data values

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11209994B2Systems and methods for data path power savings in DDR5 memory devices
Publication Date: 2021.12.28 MICRON TECHNOLOGY INC
  • US11209994B2 patent drawing
  • US11209994B2 patent drawing
  • US11209994B2 patent drawing

AI summary

A memory device includes a data path having a data bus. The memory device further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.