Inter-Die ECC Path Separation for DDR5 Write Latching
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Solution Overview
Problem
The increased clock speed in DDR5 memory devices exceeds the tolerances of existing inter-die connectors like through-silicon vias (TSVs), requiring modifications to the memory device architecture to accommodate the higher burst length, which was not effectively addressed in DDR4 designs.
Innovation Solution
The introduction of separate inter-die error correction connectors to handle error correction information separately from data connectors, allowing for faster data transfer and improved latching timing by using error correction circuitry on both master and target dies, and employing DQ double pump schemes to manage CRC bits efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the same memory device architecture of DDR4 were used in DDR5, then the data would be clocked at a higher rate, but this increased clock speed would exceed tolerances of inter-die connectors such as through-silicon vias (TSVs)
Solution Approach 1:
The patent divides the transmission path into separate channels: one for data bits and another for error correction information. This segmentation allows data to be transmitted at higher speeds while error correction bits are transmitted separately, preventing signal integrity issues that would occur if all bits shared the same high-speed path through TSVs.
Solution Approach 2:
The patent introduces separate error correction connectors as intermediary pathways that handle error correction information independently from the main data pathway. This intermediary structure allows the data pathway to operate at higher speeds without compromising the reliability of error correction transmission.
2Reliability
If separate inter-die error correction connectors are introduced, then data transfer reliability is improved, but device complexity increases
Solution Approach 1:
The separate error correction connectors serve multiple functions: they transmit error correction information between dies, provide dedicated pathways that simplify timing requirements, and enable the system to maintain higher data rates without compromising reliability. This multi-functionality justifies the additional connector structures.
Data Source
AI summary
Separate inter-die connectors for data and error correction information and related apparatuses, methods, and computing systems are disclosed. An apparatus including a master die, a target die, inter-die data connectors, and inter-die error correction connectors. The target die includes data storage elements. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct write data bits from the master die to the target die. The write data bits are written to the data storage elements. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are configured to conduct error correction information corresponding to the write data bits from the master die to the target die. The target die includes error correction circuitry configured to generate new error correction information responsive to the write data bits received from the master die.