DDR4 SDRAM Activation Counting with Reduced Row Counters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for tracking activations to rows of memory in DRAM are inefficient due to the high number of row activation counters required, leading to unmanageable power and area consumption, and the inability to accurately manage the maximum activation count (MAC) without knowing the physical orientation of rows, which results in data corruption from frequent activations.
Innovation Solution
A memory controller with a page table structure that includes two tables: RowOneAct for tracking activations during a tRCRow window and RowLeakBuck for counting activations over multiple tRCRow windows, using a reduced number of counters to manage activations and prevent data corruption by refreshing or throttling rows as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a counter is allocated for each row in each bank and rank to track activations, then the maximum activation count can be accurately tracked, but the power consumption and area requirements become unmanageable
Solution Approach 1:
The patent divides the memory controller into multiple channels, with each channel having its own activation counter. This segmentation allows the system to track activations accurately within each channel while avoiding the need for excessive counters across the entire memory system. The channel-based division reduces the area requirement by distributing the tracking function across multiple independent units rather than requiring a centralized counter for every row in every bank and rank.
Solution Approach 2:
The activation counter is designed to serve multiple rows within a channel simultaneously. Instead of dedicating one counter per row, the same counter structure is reused across multiple rows that share the same channel. This multi-functional approach allows accurate tracking of activations for multiple rows using a single counter resource, significantly reducing the total area required in the memory controller.
2Reliability
If the maximum activation count is enforced strictly, then data corruption is prevented, but the productivity of the memory system decreases due to frequent refreshes or throttling
Solution Approach 1:
The patent implements dynamic activation counting that adapts to the actual access patterns and timing. Rather than using a static, conservative MAC limit that triggers refreshes frequently, the system dynamically tracks the number of activations within the maximum activation window and only enforces the limit when actually exceeded. This dynamic approach allows the system to maintain data integrity while maximizing productivity by avoiding unnecessary refresh operations.
Solution Approach 2:
The system continuously monitors the activation count for each row and provides feedback to the memory controller. When the activation count approaches the MAC limit, the controller can proactively manage the situation by refreshing the row or throttling further activations. This feedback mechanism ensures data integrity is maintained while allowing the system to optimize productivity by making informed decisions based on real-time activation statistics rather than relying on conservative predetermined limits.
Data Source
AI summary
Efficiently tracking activations to rows of memory using a reduced number of row activation counters that indicate whether a memory row is activated during an activation period and row activation counters that indicate a number of permitted activations to a memory row within a maximum activation window.