DDR-SDRAM Controller Clock Circuitry for Write Data Alignment
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Solution Overview
Problem
DDR-SDRAM devices require complex clock signal management for data alignment during write operations, which is challenging due to narrower valid data windows and the need for independent clock signals that are not dependent on the clock frequency of other peripherals.
Innovation Solution
The implementation of a DDR-SDRAM controller that generates a 200 MHz clock signal or a 100 MHz clock delayed by ¼ of the clock period using existing DQS delay circuitry, allowing for independent data and data mask signal generation for write access, and utilizing a programmable delay line and phase-locked loop to adjust the delay for optimal data sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a 2× clock frequency signal or delayed clock signal is generated using the same clock as other peripherals, then the clock signal can be provided to the DDR-SDRAM controller, but the clock signal becomes dependent on the frequency of other peripherals, reducing flexibility and requiring additional alignment circuitry
Solution Approach 1:
The patent segments the clock signal generation into two independent paths: one path generates the system clock for peripheral devices, while another path generates the DDR-specific clock signal (either 2× frequency or delayed) using separate circuitry. This segmentation allows the DDR clock to be independently adjusted without being constrained by peripheral clock frequencies, resolving the contradiction between adaptability and complexity.
2Productivity
If the valid data window is made narrower to increase data transfer speed in DDR-SDRAM, then data transfer rate increases, but the timing alignment requirements become more stringent, increasing controller complexity
Solution Approach 1:
The patent applies preliminary action by generating the delayed clock signal (delayed by ¼ of the clock period) in advance using a delay line circuit. This pre-generated delayed clock is then used to automatically align the DQS signal with the narrow valid data window, eliminating the need for complex real-time timing adjustments and reducing controller complexity while maintaining high data transfer rates.
3Manufacturing precision
If a delayed DQS signal is used for read operations, then data alignment is achieved, but additional delay circuitry is required, increasing device complexity
Solution Approach 1:
The patent makes the delay line circuit multi-functional by designing it to serve both read and write operations. The same delay line that provides ¼ clock period delay for read operations can also generate the delayed clock signal needed for write operations. This universality reduces overall device complexity by eliminating the need for separate delay circuits for different operation types.
Data Source
AI summary
A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal.