DDR DRAM Power Down Control Without CKE Pin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DDR DRAMs require the clock enable signal CKE pin to enter or exit a power down state, which is not feasible in new DDR DRAM interfaces without this pin, limiting their ability to manage power states during self-refresh periods.
Innovation Solution
A memory system and controller that enable DDR DRAMs to enter and exit a power down state during self-refresh periods using command signals, such as entering and exiting self-refresh commands, and power down commands, without relying on the CKE pin, by utilizing a mode register and power down entry/exit bits to control the power states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CKE pin is used to control power down state, then the memory can enter/exit power down state during self-refresh, but the interface complexity increases and compatibility with new DDR interfaces without CKE pin is lost
Solution Approach 1:
The patent extracts the power down control function from the CKE pin and relocates it to command signals. Specifically, the memory controller sends command signals (such as PRE charge commands or PAUSE commands) to control the memory's power down state during self-refresh, eliminating the need for the CKE pin in new DDR interfaces while maintaining the power management capability.
2Adaptability or versatility
If command signals are used to control power down state instead of CKE pin, then compatibility with new DDR interfaces is improved, but the control precision and timing accuracy may be affected
Solution Approach 1:
The patent makes command signals multi-functional by using them for both memory operation control (such as PRE charge, PAUSE commands) and power state control simultaneously. The same command signal structure is used to trigger both the memory operation and the power down/exit transitions, eliminating the need for separate control lines while maintaining precise timing through the command signal's inherent timing characteristics.
Solution Approach 2:
The patent introduces mode register settings as intermediaries that configure the memory's response to command signals. By setting specific bits in the mode register (such as the power down entry/exit mode bits), the memory is configured to interpret certain command signals as power state transitions, providing precise control without requiring additional physical control lines.
3Loss of energy
If the memory enters power down state during self-refresh, then power consumption is reduced, but the memory operation flexibility is limited
Solution Approach 1:
The patent enables dynamic control of the power down state during self-refresh through command signals. The memory can transition between active and power down states flexibly based on system requirements, rather than being locked into a fixed power state. This allows the system to optimize power consumption while maintaining the ability to quickly resume operations when needed.
Data Source
AI summary
A memory controller is connected with a memory. The memory controller includes a clock signal pin and plural command pins. The clock signal pin is connected with the memory for transmitting a clock signal to the memory. The plural command pins are connected with the memory for transmitting a command signal to the memory. The command signal contains an entering self-refresh command and an entering power down command. The memory enters a self-refresh state when the entering self-refresh command is executed. The memory enters a power down state when the entering power down command is executed.