DDS Frequency Correction Using Dual Clock References
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Solution Overview
Problem
Existing frequency synthesizers face challenges in generating high frequency output signals with sufficient stability and accuracy, particularly as frequency increases, due to limitations in resonator manufacturing and the slow tuning capabilities of phase locked loops, while direct digital synthesizers are fast but limited in maximum output frequency and spectral purity.
Innovation Solution
A direct digital synthesizer (DDS) architecture is implemented with a local high frequency sampling clock and a local lower frequency standard, using a high frequency mmWave resonator and an oven-controlled or temperature-compensated crystal oscillator to correct for frequency errors and wander, enabling efficient frequency correction and noise filtering in the digital domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase locked loop (PLL) is used to tune the output frequency, then frequency stability is improved, but tuning speed deteriorates
Solution Approach 1:
The system is divided into two independent frequency generation paths: a PLL path for stable frequency generation and a DDS path for fast frequency switching. Each path operates autonomously, allowing the PLL to maintain stability while the DDS provides rapid tuning capability without being constrained by PLL settling time.
Solution Approach 2:
The DDS acts as an intermediary that bridges the gap between the stable but slow PLL and the application's need for fast frequency changes. The DDS can quickly switch frequencies and then the PLL can gradually settle to match, providing a transition mechanism that satisfies both stability and speed requirements.
2Speed
If a direct digital synthesizer (DDS) is used to achieve fast frequency tuning, then tuning speed is improved, but maximum output frequency is limited
Solution Approach 1:
The frequency generation task is segmented between DDS and PLL, where DDS handles low-frequency fast-switching requirements and PLL handles high-frequency stable operation. This division allows each component to operate within its optimal frequency range, with DDS providing fast tuning up to its frequency limit and PLL taking over for higher frequencies.
Solution Approach 2:
The system dynamically switches between DDS and PLL operation modes based on the required frequency and tuning speed. For low-frequency applications requiring fast changes, DDS is used; for high-frequency applications, PLL is activated. This dynamic allocation optimizes performance across the entire operating range.
3Reliability
If resonator frequency stability is improved by high manufacturing precision, then frequency stability is improved, but manufacturing difficulty increases
Solution Approach 1:
The DDS serves as an intermediary that compensates for resonator frequency variations through digital calibration. Instead of relying solely on high-precision resonator manufacturing, the system uses the DDS to measure and correct frequency deviations, thereby achieving stable output frequencies with relaxed resonator manufacturing tolerances.
Solution Approach 2:
The patent replaces reliance on mechanical/resonator precision with a digital correction system. The DDS-based frequency measurement and calibration system substitutes for the need for ultra-precise resonator manufacturing, using digital signal processing to achieve the required frequency stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the generation of accurate high frequency output signals with reduced size, weight, and power consumption, easing resonator manufacturing and enabling applications such as mmWave frequencies and distributed systems with improved frequency stability and flexibility.
Implementation Method 1
The DDS architecture corrects for frequency error (including that attributable to temperature-induced frequency variation or 'wander') of the local high frequency sampling clock using the local lower frequency standard
Implementation Method 2
the local high frequency clock is implemented using high frequency mmWave (e.g., between 1 GHz and 300 GHz) resonator to supply a free-running sampling clock to the DDS
Implementation Method 3
the local lower frequency standard is implemented with an oven controlled crystal oscillator (OCXO) or temperature compensated crystal oscillator (TCXO)
Data Source
AI summary
A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.