Phase-to-Amplitude Converter for DDS Using Segmented Logic
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Solution Overview
Problem
Direct Digital Synthesizers (DDS) face challenges in generating sine waves due to the need for large ROMs and many digital bits, leading to complex and slow systems with poor Spur-Free Dynamic Range (SFDR), especially with significant spurs at harmonics of the fundamental frequency.
Innovation Solution
The solution involves linear interpolation of the sine wave function using coarse sine functions and slope adjustments, implemented with ADD and AND arrays, reducing table sizes and logic complexity, allowing for higher-speed operation with a smaller ROM size while maintaining good SFDR performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large ROM is used to store amplitude values of the sine wave function, then the amplitude resolution and SFDR are improved, but the device complexity and cost increase significantly
Solution Approach 1:
The phase input is divided into multiple component parts (e.g., upper phase bits and lower phase bits). The sine wave function is approximated by generating partial sine and cosine functions of these component parts and combining them through multiplication and addition. This segmentation allows achieving good amplitude resolution without requiring a large ROM, as the complex sine wave generation is broken down into simpler computational steps using fewer stored values.
2Manufacturing precision
If more digital bits are used in the phase input to reduce voltage steps, then the waveform accuracy is improved, but the device complexity and processing time increase
Solution Approach 1:
Instead of using a large number of phase bits directly, the phase input is segmented into component parts. The approximation function processes these segmented parts through a series of simpler operations (partial function generation, multiplication, addition), achieving waveform accuracy comparable to or better than direct high-bit processing with reduced complexity.
Solution Approach 2:
The invention changes the parameters of the approximation function (coefficients, number of terms, segmentation points) to optimize the balance between waveform accuracy and computational complexity. By carefully selecting these parameters, the system achieves high waveform accuracy without requiring an excessive number of digital bits in the phase input.
3Measurement precision
If complex approximation functions with many adders, subtractors, and multipliers are used, then the amplitude accuracy is improved, but the operating speed decreases
Solution Approach 1:
The phase input segmentation enables the use of simpler computational operations (partial function generation from segmented parts, followed by multiplication and addition) rather than requiring complex high-precision functions. This segmentation approach maintains amplitude accuracy while reducing the complexity and number of computational stages, thereby improving operating speed.
Solution Approach 2:
The invention uses a partial approximation of the sine wave function rather than the complete exact function. By using a truncated or simplified approximation with fewer computational steps (partial action), the system achieves sufficient amplitude accuracy for practical applications while significantly improving operating speed compared to using the complete exact function.
4Device complexity
If the ROM size is reduced to lower cost, then the device complexity is reduced, but the SFDR and amplitude resolution deteriorate
Solution Approach 1:
The phase input is divided into component parts, and the sine wave is reconstructed by combining partial functions of these parts. This segmentation allows the system to use a smaller ROM (storing only coefficients for partial functions) while maintaining good SFDR performance, as the segmented approach reduces spurious components compared to simple truncation methods.
Solution Approach 2:
The invention introduces intermediary computational steps (phase splitting, partial function generation, multiplication by coefficients, and addition) between the phase input and the final sine wave output. These intermediary operations act as mediators that preserve signal quality and SFDR performance even when using a reduced-size ROM, by systematically reconstructing the sine wave from simpler components.
Data Source
AI summary
A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.