DDS-PLL Frequency Synthesizer for Fast Switching and Spur Control
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Solution Overview
Problem
Frequency synthesizers using Direct Digital Synthesizers (DDS) face challenges in achieving high-speed frequency switching with fine frequency adjustments while minimizing unnecessary frequency components and phase noise, due to spurious components generated by the clock signal's higher harmonics.
Innovation Solution
A frequency synthesizer configuration that includes a PLL circuit, DDS, clock signal supply unit, storage unit, and setting unit, where the clock signal is selected from multiple prepared frequencies to ensure that spurious components are outside a predetermined frequency range, and the dividing number of the variable frequency divider is minimized, thereby reducing unnecessary frequency components and optimizing phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal supplied to the DDS is increased to achieve high-speed frequency switching, then the switching speed is improved, but spurious components appear within the used frequency band of the DDS due to folding noise
Solution Approach 1:
The patent applies preliminary action by pre-calculating the frequencies of spurious components corresponding to the output frequency of the DDS, and preliminarily setting the dividing ratio of the program frequency divider before operation. This allows the system to avoid spurious components within the frequency band by selecting appropriate dividing ratios in advance, rather than dealing with them after they appear.
Solution Approach 2:
The patent introduces a program frequency divider as an intermediary component between the reference oscillator and the DDS. This intermediary allows for flexible adjustment of the clock signal frequency supplied to the DDS by changing the dividing ratio, enabling the system to optimize both switching speed and avoid spurious components within the operating band.
2Object-generated harmful factors
If the dividing ratio of the program frequency divider is increased to move spurious components outside the frequency band, then spurious component placement is improved, but the clock signal frequency supplied to the DDS decreases, limiting switching speed
Solution Approach 1:
The patent applies dynamics by making the dividing ratio of the program frequency divider variable rather than fixed. The control unit dynamically adjusts the dividing ratio based on the operating conditions and frequency requirements, allowing the system to optimize both spurious component placement and switching speed for different operating scenarios.
3Speed
If a high frequency clock signal is supplied to the DDS, then high-speed frequency switching is achieved, but the step width of the output frequency increases, preventing fine frequency adjustment
Solution Approach 1:
The patent applies dynamics by enabling dynamic adjustment of the dividing ratio in the program frequency divider. This allows the system to use high clock frequencies for fast switching while simultaneously achieving fine frequency adjustment by precisely controlling the dividing ratio, thereby resolving the contradiction between switching speed and frequency adjustment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high-speed frequency switching with reduced unnecessary frequency components and optimized phase noise, ensuring a stable output frequency with minimal influence from spurious components.
Implementation Method 1
a voltage control oscillator (32) that outputs the frequency signal (fVCO)
Implementation Method 2
a variable frequency divider (302) that divides the frequency signal (fVCO) output from the voltage control oscillator (32) by a dividing number (N)
Implementation Method 3
a phase comparator (301) that extracts a phase difference between a phase of the divided frequency signal and a phase of a reference frequency signal (fc)
Implementation Method 4
a loop filter (31) that supplies the voltage control oscillator (32) with a control voltage corresponding to the phase difference
Implementation Method 5
The DDS reads amplitude data from a waveform table based on phase data output corresponding to an input timing of a clock signal, thus obtaining the frequency signal of the desired frequency
Implementation Method 6
A frequency synthesizer includes a Phase Locked Loop (PLL) circuit that divides a frequency signal output from a voltage control oscillator by a frequency divider, extracts a phase difference between a phase of the divided frequency signal and a phase of a reference frequency signal by a phase comparator, and feeds a control voltage corresponding to the phase difference back to the voltage control oscillator via a loop filter
Data Source
AI summary
The present invention provides a frequency synthesizer that is switchable at a high speed and includes a few unnecessary frequency components in an output frequency signal. In a frequency synthesizer 1, a DDS 2 operates based on a clock signal to generate a reference frequency signal with a predetermined reference frequency, and clock signal supply units 41 and 42 switch the clock signals that have different clock frequencies to supply to the DDS 2. When the clock signals are switched to operate the DDS 2, the storage unit 12 stores a combination of a clock frequency fclk, a reference frequency fc, and a dividing number N in association with an output frequency fVCO of the frequency synthesizer 1 such that a spurious frequency does not exist within a predetermined frequency range and a dividing number of a variable frequency divider 302 disposed on a PLL circuit 3 is minimum. Setting units 11 and 24 read setting items stored in the storage unit 12 to set respective units.