DDS Signal Synthesizer Circuit for High-Frequency Output
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Solution Overview
Problem
Existing digital synthesizers based on direct signal synthesis (DDS) are limited to output frequencies of approximately 40% of the internal clock frequency to avoid aliasing effects, leading to high power consumption due to increased clock frequency requirements.
Innovation Solution
A signal synthesizer circuit that includes a clock source, a DDS circuit, a multiplier circuit, and a mixer circuit, allowing for the generation of output signals with frequencies higher than the clock frequency by multiplying the DDS signal and mixing it with the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to achieve higher output frequencies in a DDS synthesizer, then the output frequency range is improved, but the power consumption increases due to stray capacitances being charged and discharged in each clock cycle
Solution Approach 1:
The system segments the frequency generation process into two independent paths: a DDS path for low-frequency generation (0-40% of clock frequency) and a traditional VCO path for high-frequency generation (40%-100% of clock frequency). This segmentation allows each path to operate within its optimal frequency range, avoiding the need to increase clock frequency for high-output frequencies, thus resolving the contradiction between output frequency range and power consumption.
Solution Approach 2:
A frequency domain selection circuit acts as an intermediary that selectively routes signals from either the DDS path or the VCO path based on the desired output frequency. This mediator enables the system to achieve high output frequencies through the VCO path without increasing the clock frequency, thereby maintaining low power consumption while expanding the usable frequency range.
2Use of energy by moving object
If the clock frequency is limited to maintain low power consumption, then the power consumption is reduced, but the output frequency range is restricted to approximately 40% of the clock frequency
Solution Approach 1:
The frequency generation capability is segmented into two complementary paths: DDS circuit for 0-40% of clock frequency and VCO circuit for 40%-100% of clock frequency. This segmentation allows the system to maintain a low clock frequency for power efficiency while still providing access to high output frequencies through the VCO path, thus resolving the contradiction between power consumption and frequency range adaptability.
Solution Approach 2:
The system achieves multi-functionality by enabling a single clock frequency to support both low-frequency DDS operation and high-frequency VCO operation. The frequency domain selection circuit provides universal access to the full 0-100% clock frequency range regardless of which path is active, allowing the system to adapt to different frequency requirements without changing the clock frequency, thereby maintaining both low power consumption and high adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables the generation of output signals with frequencies significantly higher than what is achievable in existing technologies, while maintaining a given clock frequency, thus reducing power consumption and expanding the frequency range.
Implementation Method 1
the first signal path comprises a multiplier circuit being configured to multiply a frequency of the DDS signal by a multiplication factor, thereby obtaining a frequency-multiplied DDS signal
Implementation Method 2
the mixer circuit is configured to mix the clock signal with the frequency-multiplied DDS signal, thereby obtaining a mixed DDS signal, wherein a frequency of the mixed DDS signal corresponds to the sum of frequencies of the clock signal and of the frequency-multiplied DDS signal
Data Source
AI summary
A signal synthesizer circuit includes a clock source, a direct digital synthesizer (DDS) circuit, signal paths, and an output. The clock source generates or receives a clock signal having a predefined frequency. The DDS circuit generates a DDS signal. A first signal path is connected to the DDS circuit to receive the DDS signal and includes a multiplier circuit that multiplies a frequency of the DDS signal by a multiplication factor, obtaining a frequency-multiplied DDS signal. A second signal path is connected to the clock source to receive the clock signal and includes a mixer circuit that receives the clock signal and the frequency-multiplied DDS signal. The mixer circuit mixes the clock signal with the frequency-multiplied DDS signal, obtaining a mixed DDS signal. A frequency of the mixed DDS signal corresponds to the sum of frequencies of the clock signal and the frequency-multiplied DDS signal.