De-emphasis Circuit for High-Speed Serial Data Transmission
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current driver equalization designs for high-speed serial data transmission over copper lines are complex and costly, leading to increased inter-symbol interference due to attenuation and frequency dispersion, necessitating a simpler and cost-effective solution that maintains output impedance and achieves desired signal de-emphasis.
Innovation Solution
A simplified digital filter-based driver equalization system using all Nmos push-pull 50 voltage source D2A drivers with a de-emphasis unit that pre-emphasizes signal amplitudes for the first bit and de-emphasizes subsequent bits by a predetermined amount, maintaining constant output impedance and reducing inter-symbol interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex digital filter designs are used for driver equalization, then signal quality and inter-symbol interference reduction are improved, but manufacturing cost and device complexity increase substantially
Solution Approach 1:
The complex digital filter is segmented into multiple simple delay elements (D1, D2, D3) and switchable signal paths. Each delay element processes a portion of the signal with a specific delay time, and the results are combined through selective switching. This segmentation transforms a complex monolithic filter into multiple simple, manageable components that can be easily manufactured and controlled.
Solution Approach 2:
The signal is pre-processed by introducing predetermined delay times through the delay elements before the final switching and combination stage. By preliminarily delaying specific signal components and preparing them in advance, the system achieves complex filtering effects through simple, pre-configured operations rather than requiring complex real-time processing.
2Reliability
If de-emphasis is applied to subsequent bits to reduce inter-symbol interference, then signal pulse amplitude equalization is improved, but output impedance variation occurs
Solution Approach 1:
The system dynamically adjusts signal paths based on the timing and characteristics of incoming bits. The switchable architecture allows the output impedance to be dynamically optimized for each bit transition scenario, maintaining consistent impedance levels despite de-emphasis operations. The dynamic switching between different signal paths compensates for impedance variations that would otherwise occur during de-emphasis.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor output impedance levels and adjust the switching configuration accordingly. When de-emphasis is applied to subsequent bits, the feedback loop detects any impedance deviation and compensates by selecting appropriate signal paths that maintain the desired output impedance, thereby preventing harmful impedance variations.
3Manufacturing precision
If multiple digital filters are used to achieve precise de-emphasis, then manufacturing precision and signal control are improved, but manufacturing cost increases
Solution Approach 1:
Instead of manufacturing multiple complex digital filters with high precision, the invention creates simplified copies of basic delay and switching elements. These replicated simple elements (multiple identical delay elements and switches) achieve the same functional effect as a single complex filter but are much easier and cheaper to manufacture. The precision is achieved through the coordinated operation of multiple simple copies rather than a single complex component.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present invention relates to emphasizing and de-emphasizing of an analog data signal. Using a main analog driver (14) a data signal indicative of bit values of binary data is converted into a first analog data signal. A second data signal is determined by delaying the data signal a predetermined time interval and inverting the delayed data signal. Using a de-emphasis driver (114), the second data signal are converted into a second analog data signal, wherein the second analog data signal is additive to the first analog data signal if the data signal and the second data signal are indicative of a same bit value, and wherein the second analog data signal is subtractive to the first analog data signal if the data signal and the second data signal are indicative of an opposite bit value. The first analog data signal is emphasized or de-emphasized by superposing the first analog data signal and the second analog data signal.