Differential Equation Accelerator Systolic Array Parallel Processing
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Solution Overview
Problem
Current computer systems face inefficiencies in solving differential equations, particularly due to sequential calculations and limitations in parallel processing, leading to slow simulation times even on supercomputers, as described by Amdahl's law, especially for large domain sizes and complex boundary conditions.
Innovation Solution
A specialized computing architecture is designed with a system comprising an interface computer, dispatch computer, and solver units, where each solver unit includes Differential Equation Accelerators (DEAs) with multiple systolic arrays, allowing for efficient partitioning and parallel processing of sub-domains across multiple time-steps without interrupting calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential calculations are used to solve differential equations, then calculation accuracy is maintained, but simulation time becomes excessively long
Solution Approach 1:
The patent divides the computational domain into multiple sub-domains that can be processed simultaneously by different DEAs. The coordinator partitions the domain and assigns sub-domains to available DEAs, enabling parallel processing that reduces total simulation time while maintaining accuracy through consistent discretization methods across all sub-domains
Solution Approach 2:
The patent introduces a temporal dimension by implementing concurrent time-stepping where multiple DEAs process different sub-domains at the same time step. This transforms a purely sequential time-based computation into a parallel space-time computation, significantly reducing the wall-clock time required to reach solutions
2Productivity
If parallel processing is implemented to speed up calculations, then simulation time is reduced, but system complexity increases
Solution Approach 1:
The DEA architecture provides multi-functionality by incorporating multiple systolic arrays within each DEA that can handle different types of PDEs. Each DEA can be configured to solve various differential equation types using its available systolic arrays, making the parallel system versatile and adaptable to different computational problems without requiring separate specialized hardware for each equation type
Solution Approach 2:
The coordinator acts as an intermediary between the dispatch computer and multiple DEAs, managing domain partitioning, assigning sub-domains to available DEAs, and coordinating concurrent time-stepping operations. This intermediary layer simplifies the overall system architecture by centralizing control logic and abstracting the complexity of parallel coordination from individual DEAs
3Speed
If multiple DEAs process sub-domains concurrently, then calculation speed increases, but memory management complexity increases
Solution Approach 1:
The coordinator performs preliminary domain partitioning and assigns sub-domains to specific DEAs before concurrent processing begins. This pre-assignment establishes clear memory ownership and access boundaries, allowing DEAs to process their assigned sub-domains independently without complex real-time memory coordination, thus enabling high-speed concurrent processing with manageable memory access patterns
Data Source
AI summary
Embodiments relate to a computing system for solving differential equations. The system is configured to receive problem packages corresponding to problems to be solved, each comprising at least a differential equation and a domain, and to select a solver of a plurality of solvers, based upon availability of each of the plurality of solvers. Each solver comprises a coordinator that partitions the domain of the problem into a plurality of sub-domains, and assigns each of the plurality of sub-domains to a differential equation accelerator (DEA) of a plurality of DEAs. Each DEA comprises at least two memory units, and processes the sub-domain data over a plurality of time-steps by passing the sub-domain data through a selected systolic array from one memory unit, and storing the processed sub-domain data in the other memory unit, and vice versa.