Dead-Time Control for Half-Bridge Driver Circuits
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Solution Overview
Problem
Conventional dead-time control methods for half-bridge circuits are inadequate, often resulting in excessive dead-time, slower response times, and limited accuracy, which can degrade power efficiency and introduce reverse recovery currents.
Innovation Solution
A gate driver circuit with a dead-time measurement circuit that produces pulse signals to accurately measure and adaptively control dead-time between transistor turn-offs and turn-ons, using differential pairs to monitor signal transitions and adjust delay counts to minimize dead-time to nanosecond levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional dead-time control methods are used, then the circuit can operate with simple control logic, but the dead-time becomes excessively long, degrading power efficiency
Solution Approach 1:
The patent implements a feedback mechanism where the dead-time measurement circuit continuously monitors the actual dead-time duration and feeds this information back to the dead-time control circuit. The control circuit adjusts the dead-time by modifying delay counts based on the measured values, creating a closed-loop system that optimizes power efficiency while maintaining safe operation margins.
Solution Approach 2:
The patent transitions from fixed or statically adjusted dead-time to dynamically adjustable dead-time. The dead-time control circuit continuously modifies the dead-time duration by adjusting delay counts based on real-time measurements, allowing the system to adapt to varying operating conditions and minimize dead-time for improved power efficiency.
2Loss of time
If conventional adaptive dead-time detection method is used, then dead-time can be adjusted, but the circuit requires two separate comparators and additional logic circuits, increasing device complexity
Solution Approach 1:
The patent combines the functions of multiple comparators and logic circuits into a single integrated dead-time measurement circuit. This measurement circuit uses differential pairs to simultaneously monitor both transistor gate voltages and generate dead-time measurement signals, eliminating the need for separate comparators and reducing overall circuit complexity while maintaining adaptive dead-time control capability.
Solution Approach 2:
The dead-time measurement circuit serves multiple functions: it monitors gate voltages, detects transition edges, measures dead-time duration, and generates control signals for adjustment. This multi-functional design replaces what would traditionally require multiple dedicated components, simplifying the overall control circuit architecture.
3Measurement precision
If conventional circuits are used, then the control logic is simpler, but the response time is slower, resulting in loss of accuracy and resolution
Solution Approach 1:
The patent replaces conventional comparator-based detection with a differential pair-based measurement circuit. The differential pairs provide faster response times and higher precision in detecting voltage transitions and measuring dead-time duration, overcoming the speed and accuracy limitations of traditional comparator circuits.
Data Source
AI summary
A gate driver circuit includes an input terminal for receiving an input switching signal for driving a switching circuit that has a high-side transistor and a low-side transistor vertically stacked. The gate driver circuit also includes a dead-time control circuit, that includes two dead-time measurement circuits. The first dead-time measurement circuit produces a first pulse signal having a first pulse width representing a first dead-time between when a gate voltage of the low-side transistor falls below a first threshold voltage and when a gate voltage of the high-side transistor rises above a second threshold voltage. The second dead-time measurement circuit produces a second pulse signal having a second pulse width representing a second dead-time between when the gate voltage of the high-side transistor falls below the second threshold voltage and when the gate voltage of the low-side transistor rises above the second threshold voltage.