Dead-Time Locking Circuit for Stable Class D Amplifier Switching
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Solution Overview
Problem
Conventional dead-time generators in class D amplifiers are prone to variations due to temperature and process changes, leading to potential damage from excessive heat or signal distortion, as they cannot accurately lock the dead-time period.
Innovation Solution
A dead-time locking circuit comprising comparators, phase detectors, current sources, transistors, and capacitors that compare and adjust gate driving signals and output signals to maintain a consistent dead-time, preventing power transistors from turning on simultaneously and reducing signal distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional dead-time generator using only logic gates is used, then the circuit complexity is low, but the dead-time period cannot be locked and is easily affected by process and temperature variation
Solution Approach 1:
The patent implements feedback by comparing the actual dead-time period with a reference period using phase detectors and comparators. The comparison result feeds back to adjust the dead-time generator, ensuring the dead-time remains locked at the desired value despite process and temperature variations. This closed-loop feedback mechanism resolves the contradiction by providing stable dead-time control without requiring overly complex circuitry.
Solution Approach 2:
The patent changes the operating parameters by introducing voltage-controlled elements and adjustable reference voltages that allow the dead-time period to be dynamically adjusted and locked. By varying the reference voltage levels and using programmable logic arrays, the system can adapt to different process conditions and temperature ranges, maintaining reliable dead-time control.
2Productivity
If the dead-time is set too short, then the output efficiency is high, but the power transistors may turn on simultaneously causing large transient current and excessive heat
Solution Approach 1:
The patent applies preliminary action by pre-establishing the minimum safe dead-time period through the locking mechanism before the power transistors are activated. The dead-time generator ensures that sufficient time elapses between switching events, preventing simultaneous turn-on of transistors. This preliminary timing control allows the system to operate at high efficiency while inherently preventing harmful transient currents and overheating.
Solution Approach 2:
The patent introduces an intermediary dead-time control circuit that mediates between the switching signals and the power transistors. This intermediary layer enforces the minimum dead-time requirement, allowing high output efficiency to be achieved while preventing the harmful effect of simultaneous transistor activation through controlled signal timing.
3Object-affected harmful factors
If the dead-time is set too long, then the power transistors are protected from overheating, but the distortion of the output signal is increased
Solution Approach 1:
The patent implements dynamics by making the dead-time period adjustable and adaptable rather than fixed. The locking mechanism allows the dead-time to be dynamically optimized for different operating conditions, load levels, and temperature ranges. This dynamic adjustment enables the system to maintain low signal distortion while providing adequate protection against overheating, resolving the contradiction between these two requirements.
Solution Approach 2:
The patent changes parameters by allowing the dead-time duration to be varied based on operating conditions. Through programmable logic and adjustable reference voltages, the system can optimize the dead-time parameter for minimum distortion while maintaining sufficient protection margin, thereby resolving the trade-off between overheating protection and signal quality.
4Ease of manufacture
If the dead-time period is not locked, then the circuit design is simple, but the class D amplifier may be damaged by overheating or suffer from increased distortion
Solution Approach 1:
The patent uses feedback to maintain amplifier safety with minimal design complexity. The phase detectors and comparators provide automatic monitoring and adjustment of the dead-time period, ensuring it remains within safe limits without requiring complex external control circuits. This feedback-based approach preserves amplifier reliability while keeping the overall design relatively simple.
Solution Approach 2:
The patent applies self-service by enabling the dead-time generator to automatically regulate and lock its own output period. The internal feedback loop within the dead-time control circuit allows it to self-correct and maintain the proper dead-time without external intervention, ensuring amplifier safety while avoiding the need for complex external control systems.
Data Source
AI summary
The dead-time locking circuit includes phase detector and a delay-comparator. The delay-comparator includes two input ends for receiving phase adjusting signal and the input-exchanging signal received by the class D amplifier. After comparing, the delay-comparator outputs a gate driving signal. The phase detector detects the phase difference between the output signal of the class D amplifier and the gate driving signal of the power transistor of the class D amplifier, and accordingly adjusts the rising/falling edges of the gate driving signal outputted from and the comparator via the charge-pump. In this way, the dead-time can be locked at the predetermined value.